电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

7016S12JG8

产品描述Dual-Port SRAM, 16KX9, 12ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68
产品类别存储   
文件大小346KB,共21页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

7016S12JG8概述

Dual-Port SRAM, 16KX9, 12ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68

7016S12JG8规格参数

参数名称属性值
厂商名称IDT (Integrated Device Technology)
包装说明QCCJ,
Reach Compliance Codecompliant
最长访问时间12 ns
JESD-30 代码S-PQCC-J68
JESD-609代码e3
长度24.2062 mm
内存密度147456 bit
内存集成电路类型DUAL-PORT SRAM
内存宽度9
功能数量1
端子数量68
字数16384 words
字数代码16000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织16KX9
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
并行/串行PARALLEL
座面最大高度4.57 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层MATTE TIN
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
宽度24.2062 mm
Base Number Matches1

文档预览

下载PDF文档
HIGH-SPEED
16K X 9 DUAL-PORT
STATIC RAM
Features
IDT7016S/L
True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
High-speed access
– Commercial:12/15/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
Low-power operation
– IDT7016S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7016L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7016 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an
80-pin TQFP
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
13L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
14
(1,2)
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
3190 drw 01
SEM
R
(2)
INT
R
OCTOBER 2014
1
DSC 3190/11
©2014 Integrated Device Technology, Inc.

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2892  1069  1015  2005  1400  59  22  21  41  29 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved