®
XC4000A
Logic Cell Array Family
Product Specifications
Features
Description
The XC4000A family of FPGAs offers four devices at the low
end of the XC4000 family complexity range. XC4000A
differs from XC4000 in four areas: fewer routing resources,
fewer wide-edge decoders, higher output sink current, and
improved output slew-rate control.
•
Third Generation Field-Programmable Gate Arrays
–
–
–
–
–
–
–
–
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders (two per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
network
•
The XC4000 routing structure is optimized for smaller
designs, naturally requiring fewer routing resources. The
XC4000A devices have four Longlines and four single-
length lines per row and column, while the XC4000
devices have six Longlines and eight single-length lines
per row and column. This results in a smaller chip area
and lower cost per device.
•
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
•
XC4000A has two wide-edge decoders on every device
edge, while the XC4000 has four. All other wide-decoder
features are identical in XC4000 and XC4000A.
•
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
•
XC4000A outputs are specified at 24 mA, sink current,
while XC4000 outputs are specified at 12 mA. The source
current is the same 4 mA for both families.
•
Systems-Oriented Features
–
–
–
–
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (4 modes)
Programmable input pull-up or pull-down resistors
24-mA sink current per output (48 per pair)
•
The XC4000A family offers a more sophisticated output
slew-rate control structure with four configurable options
for each individual output driver: fast, medium fast, me-
dium slow, and slow. Slew-rate control can alleviate
ground-bounce problems when multiple outputs switch
simultaneously, and it can reduce or eliminate crosstalk
and transmission-line effects on printed circuit boards.
Note that the XC4003 and XC4005 devices are available in
both flavors, the lower-priced XC4003A/XC4005A with re-
duced routing, and the higher-priced XC4003/XC4005 with
more abundant routing resources. The XC4000A devices
are intended for less demanding and more structured
designs, and the XC4000 devices for more random designs
requiring additional routing resources.
The equivalent devices are pin-compatible and are avail-
able in identical packages, but they are not bitstream
compatible. In order to move from a XC4000A to a XC4000,
or vice versa, the design must be recompiled.
•
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
•
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000A Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
XC4002A
2,000
8x8
64
256
24
2,048
64
XC4003A
3,000
10 x 10
100
360
30
3,200
80
XC4004A
4,000
12 x 12
144
480
36
4,608
96
XC4005A
5,000
14 x 14
196
616
42
6,272
112
2-71
XC4000A Logic Cell Array Family
Absolute Maximum Ratings
Symbol Description
V
CC
V
IN
V
TS
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to + 150
+ 260
+ 150
Units
V
V
V
°C
°C
°C
T
STG
Storage temperature (ambient)
T
SOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
T
J
Note:
Junction temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions
for extended periods of time may affect device reliability.
Operating Conditions
Symbol
V
CC
Description
Supply voltage relative to GND Commercial 0°C to 85°C junction
Supply voltage relative to GND Industrial -40°C to 100°C junction
Supply voltage relative to GND
V
IH
V
IL
T
IN
Military –55°C to 125°C case
Min
4.75
4.5
4.5
2.0
0
Max
5.25
5.5
5.5
V
CC
0.8
250
Units
V
V
V
V
V
ns
High-level input voltage (XC4000 has TTL-like input thresholds)
Low-level input voltage (XC4000 has TTL-like input thresholds)
Input signal transition time
At junction temperatures above those listed as Operating conditions, all delay parameters increase by 0.35% per
°C.
DC Characteristics Over Operating Conditions
Symbol
V
OH
V
OL
I
CCO
I
IL
C
IN
I
RIN
I
RLL
Description
High-level output voltage @ I
OH
= –4.0 mA, V
CC
min
Low-level output voltage @ I
OL
= 24 mA, V
CC
min (Note 1)
Quiescent LCA supply current (Note 2)
Leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Horizontal Long Line pull-up (when selected) @ logic Low
0.02
0.2
–10
Min
2.4
0.4
10
+10
15
0.25
2.5
Max
Units
V
V
mA
µA
pF
mA
mA
Note: 1. With 50% of the outputs simultaneously sinking 24 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at V
CC
or GND, and
the LCA configured with a MakeBits tie option.
2-72
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Full length, both pull-ups,
inputs from IOB I-pins
Symbol
T
WAF
Device
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
-6
Max
8.5
9.0
9.5
10.0
11.5
12.0
12.5
13.0
8.5
9.0
9.5
10.0
11.5
12.0
12.5
13.0
-5
Max
7.5
8.0
8.5
9.0
10.5
11.0
11.5
12.0
7.5
8.0
8.5
9.0
10.5
11.0
11.5
12.0
PRELIMINARY
-4
Max
5.0
6.0
7.0
8.0
6.0
7.0
8.0
9.0
Max
5.7
5.8
5.9
6.0
6.7
6.8
6.9
7.0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full length, both pull-ups
inputs from internal logic
T
WAFL
Half length, one pull-up
inputs from IOB I-pins
T
WAO
Half length, one pull-up
inputs from internal logic
T
WAOL
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T
PID
)
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Global Signal Distribution
From pad through
primary
buffer, to any clock k
Symbol
T
PG
Device
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
Max
7.7
7.8
7.9
8.0
8.7
8.8
8.9
9.0
PRELIMINARY
5.1
5.5
6.3
6.7
Speed Grade
-6
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
From pad through
secondary
buffer, to any clock k
T
SG
2-73
XC4000A Logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
TBUF
driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
Symbol
T
IO1
Device
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
All devices
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
-6
Max
8.2
8.8
9.4
10.0
8.7
9.3
9.9
10.5
10.1
10.7
11.4
12.0
3.0
23.0
24.0
25.0
26.0
10.5
11.0
11.5
12.0
-5
Max
6.0
6.2
6.6
7.0
6.5
6.7
7.1
7.5
8.4
9.0
9.5
10.0
2.0
19.0
20.0
21.0
22.0
8.5
9.0
9.5
10.0
-4
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T
IO2
T going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
T going High to TBUF going inactive, not driving L.L.
T going High to L.L. going from Low to High,
pulled up by a single resistor
T
ON
T
OFF
T
PUS
T going High to L.L. going from Low to High,
pulled up by two resistors
T
PUF
2-74
PRELIMINARY
4.4
5.5
5.0
6.0
7.2
8.0
1.8
14.0
16.0
7.0
8.0
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy
between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
Speed Grade
Description
Global Clock to Output (fast)
Symbol
T
ICKOF
(Max)
Global Clock to Output (slew limited)
T
ICKO
(Max)
Input Set-up Time, using IFF (no delay)
T
PSUF
(Min)
Input Hold time, using IFF (no delay)
T
PHF
(Min)
Input Set-up Time, using IFF (with delay)
T
PSU
(Min)
Input Hold Time, using IFF (with delay)
T
PH
(Min)
Device
-6
-5
-4
Units
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
21.8
21.5
21.2
21.0
0
0
0
0
18.8
18.5
18.2
18.0
0
0
0
0
PRELIMINARY
11.6
12.0
14.6
15.0
1.6
1.2
4.0
4.5
12.0
12.0
0
0
X6091
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
14.9
15.1
15.3
15.5
19.9
20.1
20.3
20.5
2.6
2.4
2.2
2.0
4.9
5.1
5.3
5.5
12.2
12.5
12.8
13.0
15.2
15.5
15.8
16.0
2.3
2.0
1.7
1.5
3.7
4.0
4.3
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input
Set-Up
&
Hold
Time
IFF
T
PG
Global Clock-to-Output Delay
OFF
•
•
•
•
•
X3192
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture). When testing fast out-
puts, only one output switches. When testing slew-rate
limited outputs, half the number of outputs on one side of the
device are switching. These parameter values are tested
and guaranteed for worst-case conditions of supply voltage
and temperature, and also with the most unfavorable clock
polarity choice.
T
PDLI
for -4 Speed Grade
Pad to I1, I2
via transparent
latch, with delay
See page 2-76
T
PICKD
for -4 Speed Grade
Input set-up time
pad to clock (IK)
with delay
XC4003A 15.6 ns
XC4005A 15.9 ns
XC4003A 17.6 ns
XC4005A 17.9 ns
PRELIMINARY
PRELIMINARY
2-75
嵌入式系统
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