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74AC374, 74ACT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
January 2008
74AC374, 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Buffered positive edge-triggered clock
■
3-STATE outputs for bus-oriented applications
■
Outputs source/sink 24mA
■
See 273 for reset version
■
See 377 for clock enable version
■
See 373 for transparent latch version
■
See 574 for broadside pinout version
■
See 564 for broadside pinout version with inverted
General Description
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are com-
mon to all flip-flops.
outputs
■
ACT374 has TTL-compatible inputs
Ordering Information
Order
Number
74AC374SC
74AC374SJ
74AC374MTC
74AC374PC
74ACT374SC
74ACT374SJ
74ACT374MSA
74ACT374MTC
74ACT374PC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20D
MSA20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
74AC374, 74ACT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin
Names
D
0
–D
7
CP
OE
O
0
–O
7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
Truth Table
Inputs
D
n
H
L
X
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
Outputs
OE
L
L
H
CP
O
n
H
L
Z
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
2
74AC374, 74ACT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
3
74AC374, 74ACT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
= −
0.5V
V
I
=
V
CC
+
0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
−
0.5V to
+
7.0V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
±
50mA
±
50mA
−
65
°
C to
+
150
°
C
140
°
C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
4
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