HIGH-SPEED 3.3V
128K x 8 DUAL-PORT
STATIC RAM
Features
70V09L
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V09L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V09 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
◆
◆
◆
◆
◆
◆
◆
◆
◆
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
A
16L
A
0L
BUSY
R
128Kx8
MEMORY
ARRAY
70V09
17
17
Address
Decoder
Address
Decoder
A
16R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4852 drw 01
(1)
M/S
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JUNE 2019
DSC-4852/8
1
©2019 Integrated Device Technology, Inc.
70V09L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V09 is a high-speed 128K x 8 Dual-Port Static RAM. The
IDT70V09 is designed to be used as a stand-alone 1024K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads and writes to any location in memory. An automatic power down
feature controlled by the chip enables (either
CE
0
or CE
1
) permit the on-
chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 440mW of power. The IDT70V09 is
packaged in a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations
(1,2,3)
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
A
16R
GND
NC
NC
NC
NC
CE
0R
CE
1R
SEM
R
R/W
R
OE
R
GND
GND
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
GND
BUSY
L
INT
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
70V09
PNG100
(4)
100-Pin
TQFP
Top View
27
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC
NC
NC
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
1R
I/O
0R
GND
Vcc
I/O
0L
I/O1
L
GND
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
GND
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
A
16L
Vcc
NC
NC
NC
NC
CE
0L
CE
1L
SEM
L
R/W
L
OE
L
GND
NC
NC
2
4852 drw
70V09L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
16L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
16R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
4852 tbl 01
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
4852 tbl 04
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
4852 tbl 02
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
Capacitance
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0MHz)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4852 tbl 05
Output Capacitance
Maximum Operating Temperature
and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
4852 tbl 03
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
3
70V09L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable
(1,2)
CE
L
CE
0
V
IL
< 0.2V
V
IH
H
X
>V
CC
-0.2V
X
(3)
CE
1
Mode
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
4852 tbl 06
V
IH
>V
CC
-0.2V
X
V
IL
X
(3)
<0.2V
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels;
CE
is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or >V
CC
-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
4852 tbl 07
Mode
NOTES:
1. A
0L
— A
16L
≠
A
0R
— A
16R
2. Refer to Truth Table I - Chip Enable.
Truth Table III – Semaphore Read/Write Control
(1)
Inputs
CE
(2)
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
______
Mode
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Not Allowed
4852 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
7
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer toTruth Table I -
Chip Enable
.
4
70V09L
High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V09L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
CE
(2)
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4852 tbl 09
2.4
NOTES:
1. At Vcc
<
2.0V, input leakages are undefined.
2. Refer to Truth Table I -
Chip Enable
.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(5)
(V
CC
= 3.3V ± 0.3V)
70V09L15
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(2)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(2)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2)
,
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V, f = 0
(3)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(4)
,
SEM
R
=
SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outputs Disabled, f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
L
L
L
L
L
L
L
L
L
L
Typ.
(1)
145
____
70V09L20
Com'l
& Ind
Typ.
(1)
135
135
35
35
90
90
0.2
0.2
90
90
Max.
205
220
55
65
140
150
3.0
3.0
135
145
4852 tbl 10
Max.
235
____
Unit
mA
I
SB1
40
____
70
____
mA
I
SB2
100
____
155
____
mA
I
SB3
0.2
____
3.0
____
mA
I
SB4
95
____
150
____
mA
NOTES:
1. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 90mA (Typ.)
2. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
5
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