WSF128K16-XXX
128Kx16 SRAM / NOR FLASH MODULE (SMD 5962-96900**)
FEATURES
Access Times of 35ns (SRAM) and 70ns (FLASH)
Access Times of 70ns (SRAM) and 120ns (FLASH)
Packaging
• 66-pin, PGA Type, 1.075 inch square HIP, Hermetic
Ceramic HIP (Package 400)
• 68 lead, Hermetic CQFP (G1U)1, 22.4mm (0.880 inch)
square (Package 519). Designed to fit JEDEC 68 lead
0.990” CQFJ footprint (FIGURE 2)
128Kx16 5V SRAM
128Kx16 5V FLASH
Organized as 128Kx16 of SRAM and 128Kx16 of Flash
Memory with separate Data Buses
Both blocks of memory are User Configurable as 256Kx8
Low Power CMOS
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
Weight
• WSF128K16-H1X — 13 grams typical
• WSF128K16-XG1UX
1
— 5 grams typical
FLASH MEMORY FEATURES
100,000 Erase/Program Cycles minimum
Sector Architecture
• 8 equal size sectors of 16K bytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
5 Volt Programming
Embedded Erase and Program Algorithms
Page Program Operation and Internal Program Control
Time.
Note: For programming information and waveforms refer to Flash Programming 1M5 Application
Note AN0036
Note 1: Package not recommended for new designs
* This product is subject to change without notice
** For reference only. See SMD table page 10
FIGURE 1 – PIN CONFIGURATION FOR
WSF128K16-XH1X
TOP VIEW
1
SD
8
SD
9
SD
10
A
13
A
14
A
15
A
16
NC
SD
0
SD
1
SD
2
11
22
12
SWE
2
#
SCS
2
#
GND
SD
11
A
10
A
11
A
12
V
CC
SCS
1
#
NC
SD
3
33
23
SD
15
SD
14
SD
13
SD
12
OE#
NC
SWE
1
#
SD
7
SD
6
SD
5
SD
4
FD
8
FD
9
FD
10
A
6
A
7
NC
A
8
A
9
FD
0
FD
1
FD
2
44
34
V
CC
FCS
2
#
FWE
2
#
FD
11
A
3
A
4
A
5
FWE
1
#
FCS
1
#
GND
FD
3
55
45
FD
15
FD
14
FD
13
FD
12
A
0
A
1
A
2
FD
7
FD
6
FD
5
56
PIN DESCRIPTION
FD0-15
SD0-15
A0-16
SWE1-2#
SCS1-2#
OE#
V
CC
GND
NC
FWE1-2#
FCS1-2#
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
BLOCK DIAGRAM
S W E
1
# S CS
1
#
OE#
A
0-16
128K x 8
SRAM
128K x 8
SRAM
128K x 8
FLASH
128K x 8
FLASH
S W E
2
# S CS
2
#
F W E
1
# F CS
1
#
F W E
2
# F CS
2
#
8
8
8
8
FD
4
66
SD
0-7
SD
8-15
FD
0-7
FD
8-15
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF128K16-XXX
FIGURE 2 – PIN CONFIGURATION FOR
WSF128K16-XG1UX
1
FD0-15
SD0-15
PIN DESCRIPTION
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
TOP VIEW
A0-16
SWE1-2#
SCS1-2#
OE#
V
CC
GND
NC
FD
0
FD
1
FD
2
FD
3
FD
4
FD
5
FD
6
FD
7
GND
FD
8
FD
9
FD
10
FD
11
FD
12
FD
13
FD
14
FD
15
NC
A
0
A
1
A
2
A
3
A
4
A
5
FCS
1
#
GND
FCS
2
#
SWE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD
0
SD
1
SD
2
SD
3
SD
4
SD
5
SD
6
SD
7
GND
SD
8
SD
9
SD
10
SD
11
SD
12
SD
13
SD
14
SD
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
FWE1-2#
FCS1-2#
Block Diagram
S W E
1
# S CS
1
#
OE#
A
0-16
128K x 8
SRAM
S W E
2
# S CS
2
#
F W E
1
# F CS
1
#
F W E
2
# F CS
2
#
128K x 8
SRAM
128K x 8
FLASH
128K x 8
FLASH
8
8
8
8
SCS
1
#
OE#
SCS
2
#
V
CC
A
13
A
12
A
14
A
11
NC
NC
NC
SWE
2
#
FWE
1
#
FWE
2
#
NC
NC
NC
SD
0-7
SD
8-15
FD
0-7
FD
8-15
NOTE 1: Package not recommended for new designs
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF128K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Mil, Q)
Storage Temperature
Signal Voltage Relative to GND
Supply Voltage
Parameter
Flash Data Retention Mil. temp.
Flash Endurance (write/erase cycles)
Symbol
T
A
T
STG
V
G
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
7.0
7.0
Unit
°C
°C
V
V
SCS#
H
L
L
L
OE#
X
L
H
X
SRAM TRUTH TABLE
SWE#
X
H
H
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
10 years
100,000 min
Test
OE# Capacitance
F/S WE1-2# Capacitance
F/S CS1-2# Capacitance
SD0-15/FD0-15 Capacitance
A0 - A16 Capacitance
CAPACITANCE
T
A
= +25°C
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Condition
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
Max
50
20
20
20
50
Unit
pF
pF
pF
pF
pF
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil, Q)
Operating Temp. (Ind)
Operating Temp. (Com)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
T
A
Min
4.5
2.2
-0.5
-55
-40
0
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
+70
Unit
V
V
V
°C
°C
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash V
CC
Active Current for Read (1)
Flash V
CC
Active Current for Program or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Output High Voltage
Flash Low V
CC
Lock Out Voltage
Symbol
I
LI
I
LO
I
CCx16
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH1
V
OH2
V
LKO
Conditions
V
CC
= V
CC MAX
, V
IN
= GND to V
CC
SCS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
SCS# = V
IL
, OE# = FCS# = V
IH
, f = 5MHz, V
CC
= V
CC MAX
FCS# = SCS# = V
CC
± 0.5V, OE# = V
IH
, f = 5MHz, V
CC
= V
CC MAX
I
OL
= 2.1mA, V
CC
= V
CC MIN
I
OH
= -1.0mA, V
CC
= V
CC MIN
FCS# = V
IL
, OE# = SCS# = V
IH
, V
CC
= V
CC MAX
FCS# = V
IL
, OE# = SCS# = V
IH
, V
CC
= V
CC MAX
I
OL
= 8.0mA, V
CC
= V
CC MIN
I
OH
= -2.5 mA, V
CC
= V
CC MIN
I
OH
= -100
μA,
V
CC
= V
CC MIN
Min
Max
10
10
360
40
0.4
100
130
0.45
0.85 x V
CC
V
CC
-0.4
3.2
Unit
μA
μA
mA
mA
V
V
mA
mA
V
V
V
V
2.4
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 4mA/MHz, with OE# at V
IH
.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF128K16-XXX
SRAM AC CHARACTERISTICS
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
1
t
CHZ
1
t
OHZ
1
1
SRAM AC CHARACTERISTICS
-70
Max
70
0
70
35
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW1
t
WHZ1
t
DH
-35
Min
35
25
25
20
25
0
0
4
20
0
0
Max
70
60
60
30
50
5
5
5
25
-70
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-35
Min
35
35
0
35
20
0
0
20
20
Max
70
Min
25
25
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 3 – AC Test Circuit
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
V
Z
≈ 1.5V
(Bipolar Supply)
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
OH
Current Source
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF128K16-XXX
FIGURE 4 – SRAM TIMING WAVEFORM — READ CYCLE
t
RC
ADDRESS
t
RC
ADDRESS
SCS#
t
AA
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
SOE#
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (SCS# = OE# = V
IL
, SWE# = V
IH
)
READ CYCLE 2 (SWE# = V
IH
)
FIGURE 5 – SRAM WRITE CYCLE — SWE# CONTROLLED
t
WC
ADDRESS
t
AW
SCS#
t
CW
t
AH
t
AS
SWE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCLE — SCS# CONTROLLED
t
WC
ADDRESS
t
AS
SCS#
t
AW
t
CW
t
WP
t
AH
SWE#
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, SCS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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