Low Skew, 1-TO-16 LVCMOS/LVTTL
Fanout Buffer
83115
DATA SHEET
General Description
The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer
from IDT. The 83115 single-ended clock input accepts LVCMOS or
LVTTL input levels. The 83115 operates at full 3.3V supply mode
over the commercial temperature range. Guaranteed output and
part-to-part skew characteristics make the 83115 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
Sixteen LVCMOS / LVTTL outputs, 15
output impedance
One LVCMOS / LVTTL clock input
Maximum output frequency: 200MHz
All inputs are 5V tolerant
Output skew: 250ps (maximum)
Part-to-part skew: 800ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
Full 3.3V operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE2
V
DD
Pin Assignment
OE2
OE2
OE0
4
IN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
OE1
OE1
Q0
Q1
Q2
V
DD
V
DD
Q3
Q4
GND
GND
Q5
Q6
Q7
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE2
Q15
Q14
Q13
V
DD
V
DD
Q12
Q11
GND
GND
Q10
Q9
Q8
OE0
83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.5mm package body
R Package
Top View
4
OE1
GND
OE0
83115 Rev C 3/20/15
1
©2015 Integrated Device Technology, Inc.
83115 DATA SHEET
Table 1. Pin Descriptions
Number
1
2, 3, 4, 7, 8,
11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
5, 6, 23, 24
9, 10, 19, 20
14
15
Name
OE1
Q0, Q1, Q2, Q3,
Q4, Q5, Q6,
Q7, Q8, Q9,
Q10, Q11, Q12,
Q13, Q14, Q15
V
DD
GND
IN
OE0
Input
Type
Pullup
Description
Output enable pin. When LOW, forces outputs Q[2:7] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
Single-ended clock outputs. 15
output impedance.
LVCMOS/LVTTL interface levels.
Output
Power
Power
Input
Input
Pulldown
Pullup
Positive supply pins.
Power supply ground.
Single-ended clock input. 5V tolerant. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, forces outputs Q[8:13] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
Output enable pin. When LOW, forces outputs Q[0:1] and Q[14:15] to
Hi-Z state. 5V tolerant. LVCMOS/LVTTL interface levels.
See Table 3.
28
OE2
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); NOTE 1
Output Impedance
V
DD
= 3.465V
V
DD
= 3.3V
Test Conditions
Minimum
Typical
4
51
51
11
15
Maximum
Units
pF
k
k
pF
Rev C 3/20/15
2
LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
83115 DATA SHEET
Function Tables
Table 3. OEx Function Table
Inputs
OE0
0
0
0
0
1
1
1
1
OE1
0
0
1
1
0
0
1
1
OE2
0
1
0
1
0
1
0
1
Control OE2
Q[0:1], Q[14:15]
Hi-Z
Active
Hi-Z
Active
Hi-Z
Active
Hi-Z
Active
Outputs
Control OE1
Q[2:7]
Hi-Z
Hi-Z
Active
Active
Hi-Z
Hi-Z
Active
Active
Control OE0
Q[8:13]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
Active
Active
Active
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
49C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
3
Rev C 3/20/15
83115 DATA SHEET
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
OE0:OE2
Input High Voltage
IN
OE0:OE2
V
IL
Input Low Voltage
IN
OE0:OE2
I
IH
Input High Current
IN
OE0:OE2
I
IL
V
OH
V
OL
I
OZL
I
OZH
Input Low Current
IN
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Hi-Z Current Low
Output Hi-Z Current High
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.3V ± 5%
V
DD
= 3.3V ± 5%
-150
-5
2.6
0.5
5
5
-0.3
1.3
5
150
V
µA
µA
µA
µA
V
V
µA
µA
2
-0.3
Test Conditions
Minimum
2
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
DD
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Parameter
f
MAX
tjit(
tp
LH
tsk(o)
tsk(pp)
t
R
/ t
F
odc
t
EN
t
DIS
Symbol
Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time4
Output Duty Cycle
Output Enable Time
Output Disable Time
Integration Range:
12kHz – 20MHz
ƒ
200MHz
Measured on the Rising Edge
@ V
DD
/2
Measured on the Rising Edge
@ V
DD
/2
20% to 80%
400
45
1.7
0.09
2.4
150
3.1
250
800
800
55
20
20
Test Conditions
Minimum
Typical
Maximum
200
Units
MHz
ps
ns
ps
ps
ps
%
ns
ns
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Rev C 3/20/15
4
LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
83115 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
SSB Phase Noise dBc/Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Additive Phase Jitter, RMS
@ 155.52MHz (12kHz to 20MHz) =
0.09ps (typical)
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
5
Rev C 3/20/15
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