HD74LV595A
8-bit Shift Registers with 3-state Outputs
REJ03D0335–0200Z
(Previous ADE-205-281 (Z))
Rev.2.00
Jun. 28, 2004
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage
register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both
clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and
high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–16 pin (JEITA)
SOP–16 pin (JEDEC)
TSSOP–16 pin
Package Code
FP–16DAV
FP–16DNV
TTP–16DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV595AFPEL
HD74LV595ARPEL
HD74LV595ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
SER
X
X
X
L
H
X
X
X
Note: H:
L:
X:
↑:
↓:
SRCLK
SRCLR
X
X
X
X
X
L
↑
H
↑
H
↓
H
X
X
X
X
High level
Low level
Immaterial
Low to high transition
High to low transition
RCLK
X
X
X
X
X
X
↑
↓
G
H
L
X
X
X
X
X
X
Function
Force outputs into high-impedance state
Enable parallel output
Reset shift register
Shift data into shift register
Shift data into shift register
Shift register remains unchanged
Transfer shift register contents to latch register
Latch register remains unchanged
Rev.2.00 Jun. 28, 2004 page 1 of 13
HD74LV595A
Pin Arrangement
Q
B
1
Q
C
2
Q
D
3
Q
E
4
Q
F
5
Q
G
6
Q
H
7
GND 8
16 V
CC
15 Q
A
14 SER
13
G
12 RCLK
11 SRCLK
10
SRCLR
9 Q
H'
(Top view)
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
1
Output voltage range*
1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V
CC
or GND
Maximum power dissipation at
Ta = 25°C (in still air)*
3
Storage temperature
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to 7.0
–20
±50
±25
±70
785
500
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
SOP
TSSOP
Conditions
Output: H or L
Output: Z or V
CC
: OFF
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jun. 28, 2004 page 2 of 13
HD74LV595A
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Output voltage range
Output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.0
0
0
0
—
—
—
—
—
—
—
—
0
0
0
–40
Max
5.5
5.5
V
CC
5.5
–50
–2
–6
–12
50
2
6
12
200
100
20
85
Unit
V
V
V
µA
mA
Conditions
I
OL
µA
mA
Input transition rise or fall rate
∆t
/∆v
ns/V
H or L
High impedance state
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Operating free-air temperature
Ta
°C
Note: Unused or floating inputs must be held high or low.
Rev.2.00 Jun. 28, 2004 page 3 of 13
HD74LV595A
Timing Diagram
SRCLK
SER
RCLK
SRCLR
G
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H'
SHIFT
HIGH IMPEDANCE
CLEAR
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
V
IH
V
CC
(V)
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to Max
2.3
3.0
4.5
Min to Max
2.3
3.0
4.5
0 to 5.5
5.5
5.5
0
3.3
Min
1.5
V
CC
×
0.7
V
CC
×
0.7
V
CC
×
0.7
—
—
—
—
V
CC
– 0.1
2.0
2.48
3.8
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
Max
—
—
—
—
0.5
V
CC
×
0.3
V
CC
×
0.3
V
CC
×
0.3
—
—
—
—
0.1
0.4
0.44
0.55
±1
±5
20
5
—
Unit
V
Test Conditions
V
IL
Output voltage
V
OH
V
V
OL
I
OH
= –50
µA
I
OH
= –2 mA
I
OH
= –6 mA
I
OH
= –12 mA
I
OL
= 50
µA
I
OL
= 2 mA
I
OL
= 6 mA
I
OL
= 12 mA
V
IN
= 5.5 V or GND
V
O
= V
CC
or GND
V
IN
= V
CC
or GND, I
O
= 0
V
I
or V
O
= 0 to 5.5 V
V
I
= V
CC
or GND
Input current
Off-state output
current
Quiescent supply
current
Output leakage
current
Input capacitance
I
IN
I
OZ
I
CC
I
OFF
C
IN
µA
µA
µA
µA
pF
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.2.00 Jun. 28, 2004 page 5 of 13
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