D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A – NOVEMBER 1990 – REVISED APRIL 1993
•
•
•
•
•
•
•
Inputs Are TTL-Voltage Compatible
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
™
(Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
54ACT11821 . . . JT PACKAGE
74ACT11821 . . . DW PACKAGE
(TOP VIEW)
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
On the positive transition of the clock the Q outputs
will follow the D inputs.
A buffered output enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low level) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
2D
1D
OE
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
5Q
GND
GND
GND
GND
6Q
7Q
8Q
9Q
10Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
1D
2D
3D
4D
5D
V
CC
V
CC
6D
7D
8D
9D
10D
CLK
54ACT11821 . . . FK PACKAGE
(TOP VIEW)
3D
4D
5D
VCC
VCC
6D
7D
5
6
7
8
9
10
4
3 2 1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
8D
9D
10
CLK
10Q
9Q
8Q
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The 54ACT11821 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT11821 is characterized for operation form – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5Q
GND
GND
GND
GND
6Q
7Q
Copyright
©
1993, Texas Instruments Incorporated
2–1
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A – NOVEMBER 1990 – REVISED APRIL 1993
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
L
L
H
CLK
↑
↑
L
H
↓
X
D
H
L
X
X
X
X
OUTPUT
Q
H
L
Q0
Q0
X0
Z
logic symbol
†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
28
15
27
26
25
24
23
20
19
18
17
16
EN
C1
1D
1
2
3
4
5
10
11
12
13
14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
logic diagram (positive logic)
28
15
OE
CLK
1D
27
C1
1D
1
1Q
2D
26
C1
1D
2
2Q
3D
25
C1
1D
3
3Q
4D
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
24
C1
1D
4
4Q
23
C1
1D
5
5Q
6D
20
C1
1D
10
6Q
7D
19
C1
1D
11
7Q
8D
18
C1
1D
12
8Q
9D
17
C1
1D
13
9Q
Pin numbers shown are for the DW, JT, and NT packages.
10D
16
C1
1D
14
10Q
2–2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A – NOVEMBER 1990 – REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
250 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
54ACT11821
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t
/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
– 55
0
0
4.5
2
0.8
VCC
VCC
– 24
24
10
125
– 40
0
0
NOM
5
MAX
5.5
74ACT11821
MIN
4.5
2
0.8
VCC
VCC
– 24
24
10
85
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns / V
°C
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2–3
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A – NOVEMBER 1990 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50
µA
VOH
IOH = – 24 mA
IOH = – 50 mA†
IOH = – 75 mA†
IOL = 50
µA
VOL
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
II
IOZ
ICC
∆I
CC‡
Ci
Co
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
4.5
12
±0.1
±0.5
8
0.9
±1
±10
160
1
0.1
0.1
0.36
0.36
0.1
0.1
0.5
0.5
1.65
1.65
±1
±5
80
1
µA
µA
µA
mA
pF
pF
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.94
4.94
54ACT11821
MIN
4.4
5.4
3.7
4.7
3.85
3.85
0.1
0.1
0.44
0.44
V
MAX
74ACT11821
MIN
4.4
5.4
3.8
4.8
V
MAX
UNIT
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
0
4
2.5
1.5
125
54ACT11821
MIN
0
4
2.5
1.5
MAX
125
74ACT11821
MIN
0
4
2.5
1.5
MAX
125
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
125
CLK
Any Q
Any Q
Any Q
4.7
5
3.1
4.1
4.8
4.8
7.6
8.1
6.1
7.6
7.2
6.8
10.4
11
9.1
11
9.2
8.6
54ACT11821
MIN
125
4.7
5
3.1
4.1
4.8
4.8
12.6
12.9
10.8
13.2
10.6
9.8
MAX
74ACT11821
MIN
125
4.7
5
3.1
4.1
4.8
4.8
11.7
12.1
10
12.3
10.1
9.4
MAX
UNIT
MHz
ns
ns
ns
OE
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
