19-0849; Rev 0; 7/07
10-Bit LVDS Serializer
General Description
The MAX9235 serializer transforms 10-bit-wide parallel
LVCMOS/LVTTL data into a serial high-speed, low-volt-
age differential signaling (LVDS) data stream. The seri-
alizer typically pairs with deserializers like the
MAX9206, which receives the serial output and trans-
forms it back to 10-bit-wide parallel data.
The MAX9235 transmits serial data at speeds up to
400Mbps over PCB traces or twisted-pair cables. Since
the clock is recovered from the serial data stream,
clock-to-data and data-to-data skew that would be pre-
sent with a parallel bus are eliminated.
The MAX9235 serializer requires no external compo-
nents and no control signals and can lock to a 16MHz
to 40MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock.
The MAX9235 operates from a single +3.3V supply, is
specified for operation from -40°C to +105°C, and is
available in a 16-pin TQFN (3mm x 3mm) package.
Features
♦
Stand-Alone Serializer (vs. SERDES) Ideal for
Unidirectional Links
♦
Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
♦
LVDS Serial Output Rated for Point-to-Point
Applications
♦
Wide Reference Clock Input Range
16MHz to 40MHz
♦
Low 31mA Supply Current
♦
10-Bit Parallel LVCMOS/LVTTL Interface
♦
Up to 400Mbps Payload Data Rate
♦
Small 16-Pin TQFN (3mm x 3mm) Package
MAX9235
Ordering Information
PART
MAX9235ETE+
PIN-
PACKAGE
16 TQFN-EP*
REF CLOCK
RANGE (MHz)
16 to 40
PKG
CODE
TI633-5
Applications
Lane Departures
Security Cameras
Rear View Cameras
Production Line Monitoring
+Denotes
a lead-free package.
Note:
The device is specified over the -40°C to +105°C temper-
ature range.
*EP
= Exposed pad.
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit
PARALLEL-TO-SERIAL
OUT+
100Ω
OUT-
PCB OR
TWISTED PAIR
PLL
IN+
100Ω
IN-
SERIAL-TO-PARALLEL
LVDS
OUTPUT LATCH
INPUT LATCH
10
IN_
10
OUT_
TCLK
PLL
TIMING AND
CONTROL
REFCLK
TIMING AND
CONTROL
CLOCK
RECOVERY
EN
LOCK
RCLK
RCLK_R/F
MAX9235
MAX9206
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit LVDS Serializer
MAX9235
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND .........................................……………-0.3V to +4.0V
IN_, TCLK to GND ......................................-0.3V to (V
CC
+ 0.3V)
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TQFN (derate 14.7mW/°C above +70°C) ......1177mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Operating Temperature Range .........................-40°C to +105°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV
ESD Protection (Human Body Model, IN_, TCLK) ...............±2kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +105°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C,
unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
High-Level Input Voltage
Low-Level Input Voltage
Input Current
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
Change in V
OD
Between
Complementary Output States
Output Offset Voltage
Change in V
OS
Between
Complementary Output States
Output Short-Circuit Current
Power-Off Output Current
POWER SUPPLY
Supply Current
I
CC
R
L
= 100Ω or 50Ω
worst-case pattern
(Figures 2, 4)
16MHz
40MHz
22
31
35
mA
45
SYMBOL
V
IH
V
IL
I
IN
V
IN_
= 0 or V
CC
R
L
= 100Ω
R
L
= 50Ω
CONDITIONS
MIN
2.0
GND
-20
600
250
735
370
1
R
L
= 100Ω
R
L
= 50Ω
1.025
1.125
1.265
1.265
3
-13
-10
TYP
MAX
V
CC
0.8
+20
950
470
35
1.375
1.375
35
-15
+10
UNITS
V
V
µA
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, TCLK)
V
OD
ΔV
OD
V
OS
ΔV
OS
I
OS
I
OX
Figure 1
Figure 1
Figure 1
Figure 1
mV
mV
V
mV
mA
µA
OUT+ or OUT- = 0,
IN0 to IN9 = EN = high
V
CC
= 0, OUT+ or OUT- = 0 or 3.6V
2
_______________________________________________________________________________________
10-Bit LVDS Serializer
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 50Ω ±1%, C
L
= 5pF, T
A
= -40°C to +105°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless
otherwise noted.) (Notes 2, 4)
PARAMETER
TCLK Center Frequency
TCLK Frequency Variation
TCLK Period
TCLK Duty Cycle
TCLK Input Transition Time
TCLK Input Jitter
SWITCHING CHARACTERISTICS
Low-to-High Transition Time
High-to-Low Transition Time
IN_ Setup to TCLK
IN_ Hold from TCLK
PLL Lock Time
Bus LVDS Bit Width
Serializer Delay
t
LHT
t
HLT
t
S
t
H
t
PL
t
BIT
t
SD
Figure 7
t
TCP
/ 6
Figure 4
Figure 4
Figure 5
Figure 5
Figure 6
R
L
= 100Ω
R
L
= 50Ω
R
L
= 100Ω
R
L
= 50Ω
1
3
2048 x
t
TCP
t
TCP
/ 12
(t
TCP
/ 6)
+5
2049 x
t
TCP
370
350
370
350
500
500
500
500
ps
ps
ns
ns
ns
ns
ns
SYMBOL
f
TCCF
TCFV
t
TCP
TCDC
t
CLKT
t
JIT
Figure 3
CONDITIONS
MIN
16
-200
25
40
3
TYP
MAX
40
+200
62.5
60
6
150
UNITS
MHz
ppm
ns
%
ns
ps
(RMS)
MAX9235
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
,
ΔV
OD
, and V
OS
.
Note 2:
C
L
includes scope probe and test jig capacitance.
Note 3:
Parameters 100% tested at T
A
= +25°C. Limits over operating temperature range guaranteed by design and characterization.
Note 4:
AC parameters are guaranteed by design and characterization.
_______________________________________________________________________________________
3
10-Bit LVDS Serializer
MAX9235
OUT+
V
OD
OUT-
R
L
2
V
OS
R
L
2
TCLK
ODD IN_
EVEN IN_
Figure 1. Output Voltage Definitions
Figure 2. Worst-Case I
CC
Test Pattern
90%
TCLK
10%
90%
10%
3V
0
t
CLKT
t
CLKT
Figure 3. Input Clock Transition Time Requirement
5pF
OUT+
80%
R
L
V
DIFF
OUT-
5pF
t
LHT
V
DIFF
= (OUT+) - (OUT-)
t
HLT
20%
20%
80%
V
DIFF
= 0
Figure 4. Output Load and Transition Times
t
TCP
TCLK
1.5V
1.5V
1.5V
t
S
1.5V
t
H
1.5V
IN_
Figure 5. Data Input Setup and Hold Times
4
_______________________________________________________________________________________
10-Bit LVDS Serializer
MAX9235
V
CC
2.5V
2.5V
t
PL
TCLK
OUT±
HIGH IMPEDANCE
ACTIVE
HIGH IMPEDANCE
Figure 6. PLL Lock Time
IN
IN0–IN9 SYMBOL N
IN0–IN9 SYMBOL N + 1
t
SD
TCLK
1.5V
START BIT
OUT±
V
DIFF
= 0
OUT0–OUT9 SYMBOL N
STOP BIT START BIT
OUT0–OUT9 SYMBOL N + 1
STOP BIT
V
DIFF
= (OUT+) - (OUT-)
Figure 7. Serializer Delay
_______________________________________________________________________________________
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