19-3756; Rev 2; 8/10
KIT
ATION
EVALU
E
BL
AVAILA
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
General Description
The MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming
1.2W. The device also delivers 71dB ACLR for four-
carrier WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease recon-
struction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppres-
sion errors generated by analog quadrature modulators.
The MAX5898 features a f
IM
/ 4 digital image-reject
modulator. This modulator generates a quadrature-mod-
ulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at f
IM
/ 2 or f
IM
/ 4.
The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The pro-
grammable modes include the selection of 2x/4x/8x
interpolating filters, f
IM
/ 2, f
IM
/ 4 or no digital quadra-
ture modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’s-
complement data interface.
Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14-
bit CMOS, and the MAX5895 for 16-bit CMOS versions.
Features
o
71dB ACLR at f
OUT
= 61.44MHz (Four-Carrier
WCDMA)
o
Meets Multicarrier UMTS, cdma2000
®
, GSM
Spectral Masks (f
OUT
= 122MHz)
o
Noise Spectral Density = -160dBFS/Hz at
f
OUT
= 16MHz
o
90dBc SFDR at Low-IF Frequency (10MHz)
o
88dBc SFDR at High-IF Frequency (50MHz)
o
Low Power: 831mW (f
CLK
= 250MHz)
o
User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, f
IM
/ 2,
or f
IM
/ 4
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset Adjustment
o
EV Kit Available (Order the MAX5898EVKIT)
MAX5898
Ordering Information
PART
MAX5898EGK+D
MAX5898EGK-D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
68 QFN-EP*
(10mm x 10mm)
68 QFN-EP*
(10mm x 10mm)
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed paddle.
D = Dry pack
Selector Guide
PART
MAX5893
MAX5894
MAX5895
MAX5898
RESOLUTION
(BITS)
12
14
16
16
DAC UPDATE
RATE (Msps)
500
500
500
500
INPUT
LOGIC
CMOS
CMOS
CMOS
LVDS
Applications
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
Simplified Diagram
DATA PORT
DAC
OUTI
2x
INTERPOLATING
FILTERS
1x/2x/4x
INTERPOLATING
FILTERS
MODULATOR
DATA SYNCH
AND DEMUX
DATACLK
DAC
OUTQ
Pin Configuration appears at end of data sheet.
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
MAX5898
ABSOLUTE MAXIMUM RATINGS
DV
DD1.8
, AV
DD1.8
to GND, DACREF ..................-0.3V to +2.16V
AV
DD3.3
, AV
CLK
, DV
DD3.3
to GND, DACREF ........-0.3V to +3.9V
DATACLKP, DATACLKN, D0P–D15P,
D0N–D15N, SELIQP, SELIQN to GND,
DACREF ..........................................-0.3V to (DV
DD1.8
+ 0.3V)
CS, RESET,
SCLK, DIN, DOUT to
GND, DACREF ................................-0.3V to (DV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AV
DD3.3
+ 0.3V)
DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1:
Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Offset Drift
Gain Error
Gain-Error Drift
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Maximum Clock Frequency
Minimum Clock Frequency
Maximum DAC Update Rate
Minimum DAC Update Rate
Maximum Data Clock Frequency
Maximum Input Data Rate
f
CLK
f
CLK
f
DAC
f
DAC
f
DATACLK
f
DATA
f
DAC
= f
CLK
or f
DAC
= f
CLK
/ 2
f
DAC
= f
CLK
or f
DAC
= f
CLK
/ 2
Interleaved data
Per channel
f
DATA
= 125Mwps,
f
OUT
= 16MHz, f
OFFSET
= 10MHz, -12dBFS
Noise Spectral Density
f
DATA
= 125Mwps,
f
OUT
= 16MHz, f
OFFSET
= 10MHz, 0dBFS
No interpolation
2x interpolation
4x interpolation
4x interpolation
250
125
-156
-157
-157
-154
dBFS/
Hz
500
10
500
10
MHz
MHz
Msps
Msps
MHz
MWps
R
OUT
C
OUT
I
OUTFS
(Note 3)
2
-0.5
1
5
GE
FS
(Note 3)
-4
DNL
INL
OS
-0.02
16
±1
±3
±0.003
±0.03
±0.06
±110
20
+1.1
+4
+0.02
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
V
MΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
f
DATA
= 125Mwps,
interpolation off,
-0.1dBFS
In-Band SFDR
(DC to f
DATA
/ 2)
f
DATA
= 125Mwps,
2x interpolation,
-0.1dBFS
f
DATA
= 125Mwps,
4x interpolation,
-0.1dBFS
f
DATA
= 125Mwps,
f
OUT1
= 9MHz, f
OUT2
=
10MHz, -6.1dBFS
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
f
OUT
= 10MHz
f
OUT
= 30MHz
f
OUT
= 50MHz
No interpolation
2x interpolation
4x interpolation
2x interpolation,
f
IM
/ 4 complex
modulation
4x interpolation,
f
IM
/ 4 complex
modulation
79
MIN
TYP
90
84
77
89
83
92
89
83
89
-96
-99
-95
-81
dBc
MAX
UNITS
MAX5898
SFDR
f
DATA
= 125Mwps,
f
OUT1
= 79MHz,
f
OUT2
= 80MHz,
-6.1dBFS
-71
dBc
Two-Tone IMD
TTIMD
f
DATA
= 62.5Mwps,
f
OUT1
= 9MHz, f
OUT2
=
10MHz, -6.1dBFS
f
DATA
= 62.5Mwps,
f
OUT1
= 69MHz, f
OUT2
= 70MHz, -6.1dBFS
8x interpolation
-94
8x interpolation,
f
IM
/ 4 complex
modulation
-71
8x, highpass
f
DATA
= 62.5Mwps,
interpolation,
f
OUT1
= 179MHz, f
OUT2
f
IM
/ 4 complex
= 180MHz, -6.1dBFS
modulation
f
DATA
= 125Mwps, f
OUT
spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
f
DATA
= 61.44Mwps,
f
OUT
= baseband
ACLR for WCDMA
(Note 4)
f
DATA
= 122.88Mwps,
f
OUT
= 61.44MHz
f
DATA
= 122.88Mwps,
f
OUT
= 122.88MHz
4x interpolation
8x interpolation
2x interpolation,
f
IM
/ 4 complex
modulation
4x interpolation,
f
IM
/ 4 complex
modulation
-71
Four-Tone IMD
FTIMD
-89
79
79
76
dBc
ACLR
dB
68
_______________________________________________________________________________________
3
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
MAX5898
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
Output Propagation Delay
Output Rise Time
Output Fall Time
Output Settling Time
Output Bandwidth
Passband Width
SYMBOL
t
PD
t
RISE
t
FALL
CONDITIONS
1x interpolation (Note 5)
10% to 90% (Note 6)
10% to 90% (Note 6)
To 0.5% (Note 6)
-1dB bandwidth (Note 7)
Ripple < -0.01dB
0.604 x f
DATA
, 2x interpolation
Stopband Rejection
0.604 x f
DATA
, 4x interpolation
0.604 x f
DATA
, 8x interpolation
1x interpolation
Data Latency
2x interpolation
4x interpolation
8x interpolation
DAC INTERCHANNEL MATCHING
Gain Match
Gain-Match Tempco
Phase Match
Phase-Match Tempco
DC Gain Match
Crosstalk
REFERENCE
Reference Input Range
Reference Output Voltage
Reference Input Resistance
Reference Voltage Drift
CMOS LOGIC INPUTS (SCLK,
CS, RESET,
DIN)
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
CMOS LOGIC OUTPUT (DOUT)
Output High Voltage
Output Low Voltage
Output Leakage Current
V
OH
V
OL
I
LOAD
= 200µA
I
SINK
= 200µA
Tri-state
1
0.8 x
DV
DD3.3
0.2 x
DV
DD3.3
V
V
µA
V
IH
V
IL
I
IN
C
IN
-10
±0.1
3
0.7 x
DV
DD3.3
0.3 x
DV
DD3.3
+10
V
V
µA
pF
V
REFIO
R
REFIO
Internal reference
0.12
1.14
1.2
10
±50
1.32
1.28
V
V
kΩ
ppm/°C
∆Gain
∆Gain/°C
∆Phase
f
OUT
= DC - 80MHz, I
OUTFS
= 20mA
I
OUTFS
= 20mA
f
OUT
= 60MHz, I
OUTFS
= 20mA
-0.2
±0.1
±0.02
±0.13
±0.006
±0.04
-95
+0.2
dB
ppm/°C
Deg
Deg/°C
dB
dB
MIN
TYP
2.9
0.75
1
11
240
0.4 x
f
DATA
100
100
100
22
70
146
311
Clock
Cycles
dB
MAX
UNITS
ns
ns
ns
ns
MHz
∆Phase/°C
I
OUTFS
= 20mA
I
OUTFS
= 20mA (Note 3)
f
OUT
= 50MHz, f
DAC
= 250MHz
4
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
Rise/Fall Time
Differential Input Logic High
Differential Input Logic Low
Input Common-Mode Voltage
Differential Input Resistance
Input Capacitance
Differential Input Amplitude High
Differential Input Amplitude Low
Differential Output Amplitude High
Differential Output Amplitude Low
Output Common-Mode Voltage
Output Rise/Fall Time
CLOCK INPUTS (CLKP, CLKN) (Note 8)
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)
CLK to DATACLK Delay
Data Hold Time
Data Setup Time
SCLK Frequency
CS
Setup Time
Input Hold Time
Input Setup Time
Data Valid Duration
POWER SUPPLIES
Digital Supply Voltage
Digital I/O Supply Voltage
DV
DD1.8
DV
DD3.3
1.71
3.0
1.8
3.3
1.89
3.6
V
V
t
D
t
DH
t
DS
f
SCLK
t
SS
t
SDH
t
SDS
t
SDV
2.5
0
4.5
6.5
16.5
DATACLK output mode
1.65
-0.65
10
1.4
ns
ns
ns
MHz
ns
ns
ns
ns
V
COM
R
CLK
C
CLK
AC-coupled
V
DIFF
Sine-wave input
Square-wave input
> 1.5
> 0.5
> 100
AV
CLK
/
2
5
5
45
55
V
P-P
V/µs
V
kΩ
pF
%
%
V
IH
V
IL
V
ICM
R
IN
C
IN
V
IH
V
IL
V
OH
V
OL
V
OCM
R
LOAD
= 100Ω differential, C
LOAD
= 8pF,
20% to 80%
R
LOAD
= 100Ω differential (Note 3)
R
LOAD
= 100Ω differential (Note 3)
250
340
-340
1.25
0.9
-250
250
-250
1.125
1.25
110
2.5
SYMBOL
CONDITIONS
C
LOAD
= 10pF, 20% to 80%
100
-100
1.375
MIN
TYP
1.5
MAX
UNITS
ns
mV
mV
V
Ω
pF
mV
mV
mV
mV
V
ns
MAX5898
LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)
LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)
_______________________________________________________________________________________
5
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