74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 03 — 8 January 2008
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4017.
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded active
HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9),
active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous
master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see
Table 3).
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW)
independent of the clock inputs (CP0 and CP1).
Automatic code correction of the counter is provided by an internal circuit: following any
illegal code the counter returns to a proper counting mode within 11 clock pulses.
2. Features
s
Multiple package options
s
Complies with JEDEC standard no. 7 A
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC4017
74HC4017N
74HC4017D
74HC4017DB
74HC4017PW
74HC4017BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP16
SO16
SSOP16
TSSOP16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT38-4
SOT109-1
SOT338-1
Description
Version
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
SOT763-1
DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
SOT38-4
SOT109-1
74HCT4017
74HCT4017N
74HCT4017D
74HCT4017BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DHVQFN16 plastic dual in-line compatible thermal-enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
13
14
15
CP1
CP0
MR
5-STAGE JOHNSON COUNTER
DECODING AND OUTPUT CIRCUITRY
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
2
4
7
10
1
5
6
9
11
Q5-9
12
001aah242
Fig 1. Functional diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
2 of 23
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
14
13
14
CP1
CP0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
15
MR
Q7
Q8
Q9
Q5-9
001aah239
CTRDIV10/DEC
&
CT = 0
0
1
2
3
4
5
6
7
8
9
CT≥5
001aah240
3
2
4
7
10
1
5
6
9
11
12
3
2
4
7
10
1
5
6
9
11
12
13
15
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D
CP1
CP0
Q
FF
1
CP Q
RD
D
Q
FF
2
CP Q
RD
Q
FF
3
CP Q
RD
D
D
Q
FF
4
CP Q
RD
Q
FF
5
CP Q
RD
D
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig 4. Logic diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
3 of 23
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
001aah244
Fig 5. Timing diagram
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
4 of 23
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
5. Pinning information
5.1 Pinning
74HC4017
74HCT4017
74HC4017
74HCT4017
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
1
2
3
4
5
6
7
8
001aah238
terminal 1
index area
Q1
16 V
CC
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
9
Q8
Q6
Q7
Q3
5
6
7
Q0
Q2
2
3
4
16 V
CC
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
Q8
9
GND
(1)
8
GND
1
Q5
001aah241
Transparent top view
Fig 6. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 7. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
Q[0:9]
GND
Q5-9
CP1
CP0
MR
V
CC
Pin description
Pin
8
12
13
14
15
16
Description
ground (0 V)
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
clock input (LOW-to-HIGH edge-triggered)
master reset input (active HIGH)
supply voltage
3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output
74HC_HCT4017_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 8 January 2008
5 of 23
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