19-0868; Rev 0; 7/07
KIT
ATION
EVALU
E
BL
AVAILA
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
General Description
The MAX3984 is a single-channel, preemphasis driver
with input equalization that operates from 1Gbps to
10.3Gbps. It provides compensation for copper links,
such as 8.5Gbps Fibre Channel and 10.3Gbps
Ethernet, allowing spans of up to 10m with 24 AWG
cable. The driver provides four selectable preemphasis
levels, and the selectable input equalizer compensates
for up to 10in of FR-4 circuit board material at 10Gbps.
The MAX3984 also features SFP-compliant loss-of-sig-
nal (LOS) detection and TX_DISABLE. Selectable out-
put swing reduces EMI and power consumption. The
MAX3984 is packaged in a lead-free, 3mm x 3mm,
16-pin thin QFN and operates from a 0°C to +85°C tem-
perature range.
♦
Drives Up to 10m of 24 AWG Cable
♦
Drives Up to 30in of FR-4
♦
Selectable 1000mV
P-P
or 1200mV
P-P
Differential
Output Swing
♦
Selectable Output Preemphasis
♦
Selectable Input Equalization
♦
LOS Detection with Built-In Squelch
♦
Transmit Disable
♦
Hot Pluggable
Features
MAX3984
Applications
8.5Gbps Fibre Channel
10.3Gbps Ethernet
Active Cable Assemblies
STM-64
PART
MAX3984UTE+
Ordering Information
TEMP
RANGE
PIN-PACKAGE
PKG
CODE
T1633F-3
0°C to +85°C 16 Thin QFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes
a lead-free package.
*EP = Exposed pad.
Typical Operating Circuits
DISK
ENCLOSURE
ACTIVE CABLE ASSEMBLY
FABRIC SWTCH
≤
5V
R
PULLUP
≥
4.7kΩ
LOS
PE0
LOS
PE1
COPPER CABLE
DIFFERENTIAL
100Ω TWIN-AX
OUT+
GND
OUT-
0.01μF
39Ω
0.01μF
Rx+
Rx-
0.01μF
V
CC
OR
GND
OUT+
OUT-
PE0
PE1
IN_LEV
OUT_LEV
LOS
GND
+3.3V
IN+
IN-
22pF
0.01μF
LOS
22pF
0.01μF
OUT+
OUT-
22pF
39Ω
+3.3V
V
CC
IN+
IN-
PE0
0.01μF
V
CC
OR
GND
39Ω
0.01μF
22pF
IN+
IN-
GND
V
CC
OR
GND
0.01μF
+3.3V
TX_DISABLE V
CC
PE0
V
CC
OR
GND
0.01μF
PE1
IN_LEV
OUT_LEV
IN+
IN-
0.01μF
≤
10m (24 AWG)
UP TO 10Gbps
+3.3V
SWITCH
OR
SERDES
Tx+
Tx-
MAX3984
MAX3984
IN_LEV
OUT_LEV
OUT+
OUT-
SWITCH
OR
SERDES
Rx+
Rx-
0.01μF
0.01μF
Tx+
Tx-
≤
5V
≥
4.7kΩ
MAX3984
39Ω
MAX3984
PE1
IN_LEV
OUT_LEV
LOS
GND TX_DISABLE
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
MAX3984
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V
CC
).................................-0.5V to +4.1V
Continuous Output Current Range
(OUT+, OUT-) ...............................................-25mA to +25mA
Input Voltage Range (IN+, IN-) ..................-0.5V to (V
CC
+ 0.5V)
Logic Inputs Range (PE1, PE0,
TX_DISABLE, IN_LEV, OUT_LEV) ..........-0.5V to (V
CC
+ 0.5V)
LOS Open-Collector Supply Voltage Range
(with
≥
4.7kΩ pullup) .........................................-0.5V to +5.5V
Storage Ambient Temperature Range (T
STG
) ...-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
Supply Voltage
Supply Noise Tolerance
Operating Ambient Temperature
Bit Rate
Consecutive Identical Digits
(CID)
T
A
NRZ data
CID (bits)
IN_LEV = high, Figure 2;
4.25Gbps < data rate 10.3Gbps
Input Swing (Measured
differentially at data source,
point A of Figure 2 and 3. Pins
LOS and TX_DISABLE are
floating.)
IN_LEV = high, Figure 2;
1.25Gbps < data rate 4.25Gbps
IN_LEV = high, Figure 2;
1.0Gbps data rate 1.25Gbps
IN_LEV = low, Figure 3;
1.0Gbps < data rate 10.3Gbps
Time to Reach 50%
Mark/Space Ratio
360
360
360
100
SYMBOL
V
CC
1MHz
f < 2GHz
0
1.0
CONDITIONS
MIN
3.0
TYP
3.3
40
25
8.5
85
10.3
100
1200
1600
mV
P-P
2400
360
1
μs
MAX
3.6
UNITS
V
mV
P-P
°C
Gbps
Bits
2
_______________________________________________________________________________________
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
MAX3984
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at T
A
= +25°C, V
CC
= +3.3V, unless otherwise noted.)
PARAMETER
Supply Current
Inrush Current
Power-On Delay
EQUALIZER AND DRIVE SPECIFICATIONS
Input Return Loss
Input Resistance
S11
100MHz to 5GHz
Measured differentially (Note 2)
Measured differentially at point B in Figure
2; TX_DISABLE = low, OUT_LEV = high,
PE1 = PE0 = high
Different Output Swing
(Notes 3, 4)
Measured differentially at point B in Figure
2; TX_DISABLE = low, OUT_LEV = low,
PE1 = PE0 = high
TX_DISABLE = high, PE1 = PE0 = high
Common-Mode Output (AC)
(Note 4)
Output Resistance
Output Return Loss
Output Transition Time 20%
to 80%
Random Jitter (Note 4)
R
OUT
S22
t
r
, t
f
Measured at point B in Figure 2;
TX_DISABLE = low, OUT_LEV = high (Note 5)
OUT+ or OUT-, single-ended
100MHz to 5GHz
20% to 80% (Note 6)
Measured at point D in Figure 3 (Note 7)
PE1
0
Output Preemphasis
Figure 1 (Note 3)
0
1
1
Source to IN
OUT to
load
3m,
24 AWG
Residual Output Deterministic
Jitter at 1.0Gbps
(Notes 4, 8, and 9)
5m,
24 AWG
7m,
24 AWG
10m,
24 AWG
PE1
0
0
1
1
PE0
0
1
0
1
PE0
0
1
0
1
0.02
UI
P-P
3.5
6.5
9.5
13
dB
42
50
12
32
40
0.8
85
1000
10
100
115
1300
mV
P-P
800
1100
10
25
58
dB
ps
ps
RMS
mV
RMS
dB
SYMBOL
I
CC
CONDITIONS
OUT_LEV = low, TX_DISABLE = low
OUT_LEV = high, TX_DISABLE = low
Beyond steady state supply current (Note 1)
(Note 1)
1
MIN
TYP
100
120
MAX
124
148
10
30
UNITS
mA
mA
ms
6-mil, 10in of
FR-4
_______________________________________________________________________________________
3
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
MAX3984
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at T
A
= +25°C, V
CC
= +3.3V, unless otherwise noted.)
PARAMETER
SYMBOL
Source to IN
CONDITIONS
OUT to
load
3m,
24 AWG
Residual Output Deterministic
Jitter at 5.0Gbps
(Notes 4, 8, and 9)
5m,
24 AWG
7m,
24 AWG
10m,
24 AWG
Source to IN
OUT to
load
3m,
24 AWG
Residual Output Deterministic
Jitter at 8.5Gbps
(Notes 4, 8, and 9)
5m,
24 AWG
7m,
24 AWG
10m,
24 AWG
Source to IN
OUT to
load
3m,
24 AWG
Residual Output Deterministic
Jitter at 10Gbps
(Notes 4, 8, and 9)
5m,
24 AWG
7m,
24 AWG
10m,
24 AWG
Residual Output Deterministic
Jitter at 10.0Gbps
(Notes 4, 8, and 10)
Propagation Delay
STATUS OUTPUT: LOS
LOS Deassert
LOS Assert
LOS Hysteresis (Note 4)
IN_LEV = high (Note 11)
IN_LEV = low (Note 11)
IN_LEV = high (Note 11)
IN_LEV = high (Note 11)
IN_LEV = low (Note 11)
80
20
10
mV
P-P
300
100
mV
P-P
10in of FR-4 at OUT±; no
cable; see Figure 3
PE1
0
1
1
1
PE1
0
1
1
1
PE1
0
1
1
1
PE1
0
PE0
1
0
0
1
PE0
1
0
0
1
PE0
1
0
1
1
PE0
0
230
ps
0.18
0.25
UI
P-P
0.15
0.20
UI
P-P
0.09
0.12
UI
P-P
MIN
TYP
MAX
UNITS
6-mil, 10in of
FR-4
6-mil, 10in of
FR-4
6-mil, 10in of
FR-4
0.10
UI
P-P
4
_______________________________________________________________________________________
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
MAX3984
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values are at T
A
= +25°C, V
CC
= +3.3V, unless otherwise noted.)
PARAMETER
LOS Open-Collector Current
Sink
LOS Response Time
(Note 4)
SYMBOL
LOS asserted
LOS asserted; V
OL
(Note 12)
Time from V
IN
dropping below deassert level
or rising above assert level to 50% point of
LOS output transition
Rise time or fall time (10% to 90%);
pullup supply = 5.5V; external pullup
R 4.7k
200
0.4V
CONDITIONS
MIN
0
1.0
0
25
10
TYP
MAX
25
UNITS
μA
mA
μA
μs
LOS Transition Time
ns
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV
Logic-High Voltage
Logic-Low Voltage
Logic-High Current
Logic-Low Current
V
IH
V
IL
I
IH
I
IL
Current required to maintain logic-high state
at V
IH
> +2.0V
Current required to maintain logic-low state
at V
IL
< +0.8V
2.0
0.8
-150
350
V
V
μA
μA
Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured
from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.
Note 2:
IN+ and IN- are single-ended, 50Ω terminations to (V
CC
- 1.5V) ±0.2V.
Note 3:
Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 4:
Guaranteed by design and characterization.
Note 5:
PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge den-
sity) at 10Gbps. AC common-mode output is computed as:
V
ACCM_RMS
= RMS[(V
P
+ V
N
) / 2) - V
DCCM
]
where:
V
P
= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
V
N
= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (V
ACCM_RMS
) expressed as an RMS value.
DC common-mode voltage (V
DCCM
) = average DC voltage of (V
P
+ V
N
) / 2.
Note 6:
Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within
2in of the output pins with Rogers 4350 dielectric, or equivalent, and
≥
10-mil line width. For transition time, the 0% refer-
ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.
Note 7:
Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mV
P-P
differential swing. IN_LEV = logic-low and PE0 =
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band-
width) or equivalent. See Figure 3 for setup.
Note 8:
Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 9:
Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media
induced loss and not from clock source modulation. DJ is measured at point D of Figure 2.
Note 10:
Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point
A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from
media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3.
Note 11:
Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12:
True open-collector outputs. V
CC
= 0 and the external 4.7kΩ pullup resistor is connected to +5.5V.
Note 1:
_______________________________________________________________________________________
5
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