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74CBTLVD3245
8-bit level-shifting bus switch with output enable
Rev. 4 — 22 January 2016
Product data sheet
1. General description
The 74CBTLVD3245 is an 8-pole, single-throw bus switch. The device features a single
output enable input (OE) that controls eight switch channels. The switches are disabled
when OE is HIGH. Schmitt trigger action at control inputs makes the circuit tolerant of
slower input rise and fall times. This device is fully specified for partial power-down
applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging
backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 3.0 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-B/JESD36 (3.0 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLVD3245
8-bit level-shifting bus switch with output enable
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
Name
Description
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT360-1
SOT764-1
Type number
74CBTLVD3245PW
40 C
to +125
C
TSSOP20
74CBTLVD3245BQ
40 C
to +125
C
DHVQFN20 plastic dual-in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals; body
2.5
4.5
0.85 mm
4. Functional diagram
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE
19
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
B8
001aao116
Fig 1.
Logic symbol
A1
2
18
B1
9
A8
OE
19
11
B8
001aao117
Fig 2.
Logic diagram
74CBTLVD3245
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 22 January 2016
2 of 18
NXP Semiconductors
74CBTLVD3245
8-bit level-shifting bus switch with output enable
5. Pinning information
5.1 Pinning
74CBTLVD3245
terminal 1
index area
20 V
CC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
GND
(1)
GND 10
B8 11
13 B6
12 B7
n.c.
2
3
4
5
6
7
8
9
1
74CBTLVD3245
n.c.
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
001aao118
A1
A2
A3
A4
A5
A6
A7
A8
GND 10
001aao120
Transparent top view
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration for TSSOP20 (SOT360-1)
Fig 4.
Pin configuration for DHVQFN20 (SOT764-1)
5.2 Pin description
Table 2.
Symbol
n.c.
A1 to A8
GND
B1 to B8
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
not connected
data input/output (A port)
ground (0 V)
data input/output (B port)
output enable input (active LOW)
positive supply voltage
6. Functional description
Table 3.
Input
OE
L
H
[1]
Function selection
[1]
Input/output
An, Bn
An = Bn
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
74CBTLVD3245
Product data sheet
Rev. 4 — 22 January 2016
3 of 18
NXP Semiconductors
74CBTLVD3245
8-bit level-shifting bus switch with output enable
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
enable and disable mode
V
I/O
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SSOP20 and TSSOP20 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
[1]
Conditions
Min
3.0
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
V
pass
HIGH-level
input voltage
LOW-level
input voltage
input leakage
current
pass voltage
Conditions
V
CC
= 3.0 V to 3.6 V
V
CC
= 3.0 V to 3.6 V
pin OE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
V
I
= V
CC
; see
Figure 7
to
Figure 11
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
Unit
Min
2.0
-
-
-
Typ
[1]
-
-
-
-
Max
-
0.9
1
-
Min
2.0
-
-
-
Max
-
0.9
20
-
V
V
A
V
74CBTLVD3245
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 22 January 2016
4 of 18
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