74CBTLVD3244
8-bit level-shifting bus switch with 4-bit output enables
Rev. 2 — 16 December 2011
Product data sheet
1. General description
The 74CBTLVD3244 is a dual 4-pole, single-throw bus switch. The device features two
output enable inputs (nOE) that each control four switch channels. The switches are
disabled when the associated nOE input is HIGH. Schmitt trigger action at control inputs
makes the circuit tolerant of slower input rise and fall times. This device is fully specified
for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 3.0 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-B/JESD36 (3.0 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLVD3244
8-bit level-shifting bus switch with 4-bit output enables
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74CBTLVD3244DS
Name
Description
plastic shrink small outline package; 20 leads; body
width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT724-1
SOT360-1
SOT764-1
Type number
40 C
to +125
C
SSOP20
[1]
74CBTLVD3244PW
40 C
to +125
C
TSSOP20
74CBTLVD3244BQ
40 C
to +125
C
DHVQFN20 plastic dual-in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals; body
2.5
4.5
0.85 mm
[1]
Also known as QSOP20 package
4. Functional diagram
1A1
2
1OE
1
1A2
4
1A3
6
1A4
8
18
1B1
16
1B2
14
1B3
12
1B4
2A1
11
2OE
19
2A2
13
2A3
15
2A4
17
9
2B1
7
2B2
5
2B3
3
2B4
001aan303
Fig 1.
Logic symbol
74CBTLVD3244
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
2 of 20
NXP Semiconductors
74CBTLVD3244
8-bit level-shifting bus switch with 4-bit output enables
1A1
1B1
1A4
1OE
2A1
1B4
2B1
2A4
2OE
2B4
001aan196
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
74CBTLVD3244
74CBTLVD3244
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1B1
17 2A4
16 1B2
15 2A3
14 1B3
13 2A2
12 1B4
11 2A1
aaa-000025
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
1
2
3
4
5
6
7
8
9
20
V
CC
19 2OE
18 1B1
17 2A4
16 1B2
15 2A3
14 1B3
13 2A2
12 1B4
11 2A1
GND 10
GND 10
aaa-000026
Fig 3.
Pin configuration for TSSOP20 (SOT360-1)
Fig 4.
Pin configuration for SSOP20 (SOT724-1)
74CBTLVD3244
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
3 of 20
NXP Semiconductors
74CBTLVD3244
8-bit level-shifting bus switch with 4-bit output enables
74CBTLVD3244
1OE
1
1A1 2
2B4 3
1A2 4
2B3 5
1A3 6
2B2 7
1A4 8
2B1 9
GND 10
2A1 11
aaa-000027
terminal 1
index area
20 V
CC
19 2OE
18 1B1
17 2A4
16 1B2
15 2A3
14 1B3
13 2A2
12 1B4
GND
(1)
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5.
Pin configuration for DHVQFN20 (SOT764-1)
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1A1 to 1A4
2B1 to 2B4
GND
2A1 to 2A4
1B1 to 1B4
V
CC
Pin description
Pin
1, 19
2, 4, 6, 8
9, 7, 5, 3
10
11, 13, 15, 17
18, 16, 14, 12
20
Description
output enable input (active LOW)
data input/output (A port)
data input/output (A port)
ground (0 V)
data input/output (B port)
data input/output (B port)
positive supply voltage
6. Functional description
Table 3.
Input
nOE
L
H
[1]
Function selection
[1]
Input/output
nAn, nBn
nAn = nBn
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74CBTLVD3244
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
4 of 20
NXP Semiconductors
74CBTLVD3244
8-bit level-shifting bus switch with 4-bit output enables
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
enable and disable mode
V
I/O
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SSOP20 and TSSOP20 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
[1]
Conditions
Min
3.0
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
V
pass
HIGH-level
input voltage
Conditions
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +125
C
Unit
Min
2.0
-
-
-
Typ
[1]
-
-
-
-
Max
-
0.9
1
-
Min
2.0
-
-
-
Max
-
0.9
20
-
V
V
A
V
LOW-level input V
CC
= 3.0 V to 3.6 V
voltage
input leakage
current
pass voltage
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
V
I
= V
CC
; see
Figure 8
to
Figure 12
74CBTLVD3244
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 16 December 2011
5 of 20
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