74CBTLV3253
Dual 1-of-4 multiplexer/demultiplexer
Rev. 4 — 15 December 2011
Product data sheet
1. General description
The 74CBTLV3253 provides a dual 1-of-4 high-speed multiplexer/demultiplexer with two
common select inputs (S0, S1) and two output enable inputs (1OE, 2OE). The low ON
resistance of the switch allows inputs to be connected to outputs without adding
propagation delay or generating additional ground bounce noise. When pin nOE = LOW,
one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When
pin nOE = HIGH, all switches are in the high-impedance OFF-state, independent of pins
S0 and S1.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the V
CC
through a pull-up resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLV3253
Dual 1-of-4 multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74CBTLV3253D
74CBTLV3253DS
74CBTLV3253PW
74CBTLV3253BQ
40 C
to +125
C
40 C
to +85
C
40 C
to +125
C
40 C
to +125
C
SO16
SSOP16
[1]
TSSOP16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT519-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual-in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals; body
2.5
3.5
0.85 mm
[1]
Also known as QSOP16.
4. Functional diagram
1A
7
6
1B1
5
1B2
4
1B3
3
1B4
2A
9
10
2B1
11
2B2
12
2B3
13
2B4
S0
14
S1
2
1OE
1
2OE
15
001aal208
Fig 1.
74CBTLV3253
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 15 December 2011
2 of 19
NXP Semiconductors
74CBTLV3253
Dual 1-of-4 multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
74CBTLV3253
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
001aal209
74CBTLV3253
1OE
2
3
4
5
6
7
8
GND
2A
9
GND
(1)
1
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
001aal210
terminal 1
index area
74CBTLV3253
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
S1
1B4
1B3
1B2
1B1
1A
001aal211
Transparent top view
(1) This is not a supply pin. The
substrate is attached to this pad
using conductive die attach
material. There is no electrical or
mechanical requirement to
solder this pad. However, if it is
soldered, the solder land should
remain floating or be connected
to GND.
Fig 2.
Pin configuration
SOT109-1 (SO16) and
SOT519-1 (SSOP16)
Fig 3.
Pin configuration
SOT403-1 (TSSOP16)
Fig 4.
Pin configuration
SOT763-1 (DHVQFN16)
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
S0, S1
1B1 to 1B4
2B1 to 2B4
GND
1A, 2A
V
CC
Pin description
Pin
1, 15
14, 2
6, 5, 4, 3
10, 11, 12, 13
8
7, 9
16
Description
output enable input (active LOW)
select input
B input/output
B input/output
ground (0 V)
A input/output
supply voltage
74CBTLV3253
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 15 December 2011
3 of 19
NXP Semiconductors
74CBTLV3253
Dual 1-of-4 multiplexer/demultiplexer
6. Functional description
Table 3.
Inputs
1OE
X
H
L
L
L
L
[1]
Function table
[1]
Function switch
2OE
H
X
L
L
L
L
S1
X
X
L
L
H
H
S0
X
X
L
H
L
H
disconnect 2A and 2Bn
disconnect 1A and 1Bn
1A to 1B1 and 2A to 2B1
1A to 1B2 and 2A to 2B2
1A to 1B3 and 2A to 2B3
1A to 1B4 and 2A to 2B4
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
control inputs
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
[2]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
The switch voltage ratings may be exceeded if switch clamping current ratings are observed
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.3 V to 3.6 V
[1]
Conditions
Min
2.3
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
74CBTLV3253
Product data sheet
Rev. 4 — 15 December 2011
4 of 19
NXP Semiconductors
74CBTLV3253
Dual 1-of-4 multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
I
S(OFF)
I
S(ON)
I
OFF
I
CC
HIGH-level
input voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
Min
1.7
2.0
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
1
1
1
10
10
T
amb
=
40 C
to +125
C
Unit
Min
1.7
2.0
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
20
20
20
50
50
V
V
V
V
A
A
A
A
A
LOW-level input V
CC
= 2.3 V to 2.7 V
voltage
V
CC
= 3.0 V to 3.6 V
input leakage
current
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
OFF-state
V
CC
= 3.6 V; see
Figure 5
leakage current
ON-state
V
CC
= 3.6 V; see
Figure 6
leakage current
power-off
V
I
or V
O
= 0 V to 3.6 V;
leakage current V
CC
= 0 V
supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
I
= V
CC
0.6 V;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
CC
= 3.3 V;
V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
[2]
I
CC
additional
supply current
input
capacitance
OFF-state
capacitance
ON-state
capacitance
-
-
300
-
2000
A
C
I
C
S(OFF)
C
S(ON)
-
-
-
0.9
5.2
20.0
-
-
-
-
-
-
-
-
-
pF
pF
pF
[1]
[2]
All typical values are measured at T
amb
= 25
C.
One input at 3 V, other inputs at V
CC
or GND.
9.1 Test circuits
V
CC
V
IH
Is
V
CC
V
IL
Is
Is
nOE
nBn
GND
nA
nOE
nA
GND
nBn
VO
A
Vl
A
VO
Vl
A
001aai101
001aai103
V
I
= V
CC
or GND and V
O
= GND or V
CC
.
V
I
= V
CC
or GND and V
O
= open circuit.
Fig 5.
Test circuit for measuring OFF-state leakage
current (one switch)
Fig 6.
Test circuit for measuring ON-state leakage
current (one switch)
74CBTLV3253
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 15 December 2011
5 of 19
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
