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74CBTLVD3861
10-bit level-shifting bus switch with output enable
Rev. 4 — 14 December 2011
Product data sheet
1. General description
The 74CBTLVD3861 is a 10-bit 3.3 V to 1.8 V level translating bus switch with one output
enable (OE) input. When OE is LOW, the switch is closed and port A is connected to the B
port. When OE is HIGH, the switch is disabled.
To ensure the high-impedance OFF-state during power-up or power-down, OE should be
tied to the V
CC
through a pull-up resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 3.0 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
2. Features and benefits
Supply voltage range from 3.0 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-B/JESD36 (3.0 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
4
switch connection between two ports
3.3 V to 1.8 V level translation
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74CBTLVD3861DK
Name
Description
plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT556-1
SOT355-1
SOT815-1
Type number
40 C
to +125
C
SSOP24
[1]
74CBTLVD3861PW
40 C
to +125
C
TSSOP24
74CBTLVD3861BQ
40 C
to +125
C
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
[1]
Also known as QSOP24 package
4. Functional diagram
A1
2
OE
23
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
22
B1
21
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
B9
13
B10
001aan142
Fig 1.
Logic symbol
A1
2
22
B1
A10
OE
11
23
13
B10
001aam471
Fig 2.
Logic diagram
74CBTLVD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 14 December 2011
2 of 19
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
5. Pinning information
5.1 Pinning
74CBTLVD3861
n.c.
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
24 V
CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
001aan152
74CBTLVD3861
n.c.
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
24 V
CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
001aan153
A9 10
A10 11
GND 12
A9 10
A10 11
GND 12
Fig 3.
Pin configuration for TSSOP24 (SOT355-1)
Fig 4.
Pin configuration for SSOP24 (SOT556-1)
74CBTLVD3861
terminal 1
index area
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
GND
(1)
GND 12
B10 13
24 V
CC
23 OE
22 B1
21 B2
20 B2
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
n.c.
1
A9 10
A10 11
001aan154
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5.
Pin configuration for DHVQFN24 (SOT815-1)
74CBTLVD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 14 December 2011
3 of 19
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
5.2 Pin description
Table 2.
Symbol
nc
A1 to A10
GND
B1 to B10
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12
23
24
Description
not connected
data input/output (A port)
ground (0 V)
output enable input (active LOW)
positive supply voltage
22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port)
6. Functional description
Table 3.
Input
OE
L
H
[1]
Function selection
[1]
Input/output
An, Bn
An = Bn
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SSOP24 and TSSOP24 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN24 package: P
tot
derates linearly at 4.5 mW/K above 60
C.
74CBTLVD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 14 December 2011
4 of 19
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