74CBTLV3126-Q100
4-bit bus switch
Rev. 1 — 3 April 2013
Product data sheet
1. General description
The 74CBTLV3126-Q100 provides a 4-bit high-speed bus switch with separate output
enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections
to be made with minimal propagation delay. The switch is disabled (high-impedance
OFF-state) when the output enable (nOE) input is LOW.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the GND through a pull-down resistor. The current-sinking capability of the driver
determines the minimum value of the resistor.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Supply voltage range from 2.3 V to 3.6 V
Standard ’126’-type pinout
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
NXP Semiconductors
74CBTLV3126-Q100
4-bit bus switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74CBTLV3126PW-Q100
40 C
to +125
C
74CBTLV3126BQ-Q100
40 C
to +125
C
TSSOP14
Description
plastic thin shrink small outline package; 14
leads; body width 4.4 mm
Version
SOT402-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14
terminals; body 2.5
3
0.85 mm
4. Functional diagram
1OE
1A
2OE
2A
3OE
3A
4OE
4A
4B
001aaj023
1B
2B
3B
nA
nB
nOE
001aal245
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
2 of 16
NXP Semiconductors
74CBTLV3126-Q100
4-bit bus switch
5. Pinning information
5.1 Pinning
&%7/94
2(
*1'
%
*1'
WHUPLQDO
LQGH[ DUHD
9
&&
2(
$
%
2(
$
&%7/94
2(
$
%
2(
$
%
*1'
DDD
$
9
&&
2(
$
%
2(
$
%
%
2(
$
%
DDD
7UDQVSDUHQW WRS YLHZ
This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration SOT402-1 (TSSOP14)
Fig 4.
Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1OE to 4OE
1A to 4A,
1B to 4B
GND
V
CC
n.c.
Pin description
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
-
Description
output enable input
A input/output
B output/input
ground (0 V)
positive supply voltage
not connected
6. Functional description
Table 3.
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Function switch
OFF-state
ON-state
Output enable input OE
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
3 of 16
NXP Semiconductors
74CBTLV3126-Q100
4-bit bus switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
control inputs
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
[2]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
The switch voltage ratings may be exceeded if switch clamping current ratings are observed
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
pin nOE; V
CC
= 2.3 V to 3.6 V
control inputs
enable and disable mode
Conditions
Min
2.3
0
0
40
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
I
S(OFF)
HIGH-level
input voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
Min
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
Max
-
-
0.7
0.9
1.0
1
T
amb
=
40 C
to +125
C
Unit
Min
1.7
2.0
-
-
-
-
Max
-
-
0.7
0.9
20
20
V
V
V
V
A
A
LOW-level input V
CC
= 2.3 V to 2.7 V
voltage
V
CC
= 3.0 V to 3.6 V
input leakage
current
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
OFF-state
V
CC
= 3.6 V; see
Figure 5
leakage current
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
4 of 16
NXP Semiconductors
74CBTLV3126-Q100
4-bit bus switch
Table 6.
Static characteristics
…continued
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
S(ON)
I
OFF
I
CC
Conditions
T
amb
=
40 C
to +85
C
Min
ON-state
V
CC
= 3.6 V; see
Figure 6
leakage current
power-off
V
I
or V
O
= 0 V to 3.6 V;
leakage current V
CC
= 0 V
supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
I
= V
CC
0.6 V;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
CC
= 3.3 V;
V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
[2]
T
amb
=
40 C
to +125
C
Unit
Min
-
-
-
Max
20
50
50
A
A
A
Typ
[1]
-
-
-
Max
1
10
10
-
-
-
I
CC
additional
supply current
input
capacitance
OFF-state
capacitance
ON-state
capacitance
-
-
300
-
2000
A
C
I
C
S(OFF)
C
S(ON)
-
-
-
0.9
5.2
14.3
-
-
-
-
-
-
-
-
-
pF
pF
pF
[1]
[2]
All typical values are measured at T
amb
= 25
C.
One input at 3 V, other inputs at V
CC
or GND.
9.1 Test circuits
V
CC
nOE
IS
V
CC
nOE
A
VO
VI
IS
V
IL
A
VI
IS
V
IH
nB
nA
GND
A
nA
nB
GND
VO
001aal249
001aal250
V
I
= V
CC
or GND and V
O
= GND or V
CC
.
V
I
= V
CC
or GND and V
O
= open circuit.
Fig 5.
Test circuit for measuring OFF-state leakage
current (one switch)
Fig 6.
Test circuit for measuring ON-state leakage
current (one switch)
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
5 of 16
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