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74CBTLV3125-Q100
4-bit bus switch
Rev. 1 — 5 January 2017
Product data sheet
1. General description
The 74CBTLV3125-Q100 is a 4-bit high-speed bus switch with separate output enable
inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be
made with minimal propagation delay. The switch is disabled (high-impedance OFF-state)
when the output enable (nOE) input is HIGH.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the V
CC
through a pull-up resistor. The minimum value of the resistor is determined
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Supply voltage range from 2.3 V to 3.6 V
Standard ’125’-type pinout
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
NXP Semiconductors
74CBTLV3125-Q100
4-bit bus switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74CBTLV3125PW-Q100
40 C
to +125
C
Description
Version
SOT402-1
Type number
TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 mm
[1]
Also known as QSOP16.
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration SOT402-1 (TSSOP14)
74CBTLV3125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 5 January 2017
2 of 16
NXP Semiconductors
74CBTLV3125-Q100
4-bit bus switch
5.2 Pin description
Table 2.
Symbol
1OE, 2OE, 3OE, 4OE
1A, 2A, 3A, 4A,
1B, 2B, 3B, 4B
GND
V
CC
Pin description
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
output enable input
A input/output
B output/input
ground (0 V)
positive supply voltage
6. Functional description
Table 3.
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Function switch
ON-state
OFF-state
Output enable input OE
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
control inputs
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
[2]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
500
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
The switch voltage ratings may be exceeded if switch clamping current ratings are observed
For TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
74CBTLV3125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 5 January 2017
3 of 16
NXP Semiconductors
74CBTLV3125-Q100
4-bit bus switch
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
pin nOE; V
CC
= 2.3 V to 3.6 V
control inputs
enable and disable mode
Conditions
Min
2.3
0
0
40
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
I
I
I
S(OFF)
I
S(ON)
I
OFF
I
CC
HIGH-level
input voltage
Conditions
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
T
amb
=
40 C
to +85
C
Min
1.7
2.0
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
1.0
1
1
10
10
T
amb
=
40 C
to +125
C
Unit
Min
1.7
2.0
-
-
-
-
-
-
-
Max
-
-
0.7
0.9
20
20
20
50
50
V
V
V
V
A
A
A
A
A
LOW-level input V
CC
= 2.3 V to 2.7 V
voltage
V
CC
= 3.0 V to 3.6 V
input leakage
current
pin nOE; V
I
= GND to V
CC
;
V
CC
= 3.6 V
OFF-state
V
CC
= 3.6 V; see
Figure 4
leakage current
ON-state
V
CC
= 3.6 V; see
Figure 5
leakage current
power-off
V
I
or V
O
= 0 V to 3.6 V;
leakage current V
CC
= 0 V
supply current
V
I
= GND or V
CC
; I
O
= 0 A;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
I
= V
CC
0.6 V;
V
SW
= GND or V
CC
;
V
CC
= 3.6 V
pin nOE; V
CC
= 3.3 V;
V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
V
CC
= 3.3 V; V
I
= 0 V to 3.3 V
[2]
I
CC
additional
supply current
input
capacitance
OFF-state
capacitance
ON-state
capacitance
-
-
300
-
2000
A
C
I
C
S(OFF)
C
S(ON)
-
-
-
0.9
5.2
14.3
-
-
-
-
-
-
-
-
-
pF
pF
pF
[1]
[2]
All typical values are measured at T
amb
= 25
C.
One input at 3 V, other inputs at V
CC
or GND.
74CBTLV3125_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 5 January 2017
4 of 16
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