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74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7-A.
The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active
HIGH output enable inputs.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger action
Inputs accept voltages higher than V
CC
Input levels:
N
The 74VHC126 operates with CMOS input level
N
The 74VHCT126 operates with TTL input level
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74VHC126D
74VHCT126D
74VHC126PW
74VHCT126PW
74VHC126BQ
74VHCT126BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
4. Functional diagram
2
1
5
4
9
10
12
13
1A
1OE
2A
2OE
3A
3OE
4A
4OE
1Y
3
2Y
6
3Y
8
4Y
11
mna235
Fig 1.
Functional diagram
2
1
5
EN1
1
3
6
4
9
8
10
nA
nY
12
11
13
nOE
mna234
mna236
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74VHC_VHCT126_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
2 of 15
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74VHC126
74VHCT126
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
001aak056
74VHC126
74VHCT126
1OE
2
3
4
5
6
7
GND
3Y
8
GND
(1)
1
13 4OE
12 4A
11 4Y
10 3OE
9
8
3A
3Y
14 V
CC
terminal 1
index area
1A
1Y
2OE
2A
2Y
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9
3A
001aak076
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
output enable input 1 (active HIGH)
data input 1
data output 1
output enable input 2 (active HIGH)
data input 2
data output 2
ground (0 V)
data output 3
data input 3
output enable input 3 (active HIGH)
data output 4
data input 4
output enable input 4 (active HIGH)
supply voltage
74VHC_VHCT126_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
3 of 15
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
6. Functional description
Table 3.
Control
nOE
H
H
L
[1]
H = HIGH voltage state;
L = LOW voltage state;
X = don’t care;
Z = high-impedance OFF-state.
Function table
[1]
Input
nA
L
H
X
Output
nY
L
H
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
74VHC_VHCT126_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 13 August 2009
4 of 15
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