Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
Feedback input to phase detector
Input for external loop filter connection
Clock outputs
Inverted clock output
Clock output (2 x Q frequency)
Clock output (Q frequency ÷ 2)
Indicates phase lock has been achieved (HIGH when locked)
Asynchronous reset (active LOW)
Disables phase-lock for low frequency testing (refer to functional block diagram)
2
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
A
T
BIAS
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
StorageTemperature
DC Output Current
Max.
–0.5 to 7
–0.5 to V
CC
+0.5
0 to +70
–55 to +125
–55 to +125
–60 to 120
Unit
V
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Outputs and I/O terminals.
SYNC INPUT TIMING REQUIREMENTS
Symbol
T
RISE/FALL
Frequency
Duty Cycle
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2.0V)
Input Frequency, SYNC Inputs
Input Duty Cycle, SYNC Inputs
Min.
—
10
25%
Max.
3
2Q fmax
75%
Unit
ns
MHz
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to 70°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
I
IH
I
IL
V
IK
V
IH
V
OH
V
OL
I
CCL
I
CCH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
Input Hysteresis
Output HIGH Voltage
Output LOW Voltage
Quiescent Power Supply Current
V
CC
= Min.
V
CC
= Min.
V
CC
= Max., V
IN
= GND or V
CC
(Test mode, LF connected to GND)
V
CC
= Min., I
IN
= –18mA
—
I
OH
= –15mA
I
OL
= 64mA
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
Min.
2
—
—
—
—
—
2.4
—
—
Typ.
(2)
—
—
—
—
–0.7
100
3.5
0.2
2
Max.
—
0.8
±1
±1
–1.2
—
—
0.55
4
Unit
V
V
µA
µA
V
mV
V
V
mA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
3
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
C
PD
I
C
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Power Dissipation Capacitance
Total Power Supply Current
(5,6)
Test Conditions
(1)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
V
IN
= V
CC
All Outputs Open
V
IN
= GND
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50pF.
All other outputs open.
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. Q4 loaded with 50Ω
Thevenin termination. All other outputs open.
50Ω Thevenin termination @ 33MHz
50Ω Paralell termination to GND @ 33MHz
Min.
—
—
—
—
Typ.
(2)
0.5
0.5
25
65
Max.
1.5
0.7
40
80
Unit
mA
mA/
MHz
pF
mA
—
—
—
mA
P
D1
P
D2
Power Dissipation
Power Dissipation
—
—
120
300
—
—
mW
mW
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
I
LOAD
= Dynamic Current due to load.
OUTPUT FREQUENCY SPECIFICATIONS
Max.
(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4,
Q5
Outputs
Operating frequency Q/2 Output
Min.
40
20
10
55
55
27.5
13.75
70
70
35
17.5
100
100
50
25
133
133
66.7
33.3
Unit
MHz
MHz
MHz
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
4
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
RISE/FALL
All Outputs
t
RISE/FALL
2Q Output
(3)
t
PULSE WIDTH
Q,
Q,
Q/2 Outputs
(3)
t
PULSE WIDTH
2Q Output
(3)
t
PULSE WIDTH
2Q Output
(3)
t
PD
SYNC-FEEDBACK
(3)
t
SKEWr
(rising)
(3, 4)
t
SKEWf
(falling)
(3, 4)
t
SKEW
ALL
(3, 4)
t
LOCK(6)
t
RST
Reset – Q
t
REC(10)
t
W(10)
Parameter
Rise/Fall Time
(between 0.2 V
CC
and 0.8 V
CC
)
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4,
Q5,
Q/2 @ V
CC
/2
Output Pulse Width
2Q Output @ V
CC
/2
Output Pulse Width
2Q @ 1.5V
SYNC input to FEEDBACK delay
(measured at SYNC0 or 1 and FEEDBACK
input pins)
Output to Output Skew between outputs 2Q,
Q0-Q4,Q/2 (rising edges only)
Output to Output Skew between outputs 2Q,
Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising,
Q5
falling
Time required to acquire Phase-Lock from time
SYNC input signal is received
Propagation Delay,
RST
(HIGH-to-LOW) to any
Output (HIGH-to-LOW)
Reset Recovery Time
Rising
RST
edge to falling SYNC edge
Minimum Pulse Width
RST
input LOW
5
—
ns
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, C
L
= 50pF (±2pF), and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q,
Q,
Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin. t
LOCK
Max. is with C1 = 0.1µF, t
LOCK
Min. is with C1 = 0.01µF (where C1 is loop filter
capacitor shown in Figure 2).
7. These two specs ( t
RISE/FALL
and t
PULSE WIDTH
2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed
by IDT, the termination scheme shown in Figure 1 must be used:
NXP MCU
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