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74VHCT373A Octal D-Type Latch with 3-STATE Outputs
May 2007
74VHCT373A
Octal D-Type Latch with 3-STATE Outputs
Features
■
High speed: t
PD
=
7.7ns (Typ.) at T
A
=
25°C
■
High Noise Immunity: V
IH
=
2.0V, V
IL
=
0.8V
■
Power Down Protection is provided on all inputs and
tm
General Description
The VHCT373A is an advanced high speed CMOS octal
D-type latch with 3-STATE output fabricated with silicon
gate CMOS technology. It achieves the high speed oper-
ation similar to equivalent Bipolar Schottky TTL while
maintaining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an output enable input (OE). The latches appear
transparent to data when latch enable (LE) is HIGH.
When LE is LOW, the data that meets the setup time is
latched. When the OE input is HIGH, the eight outputs
are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output
(1)
pins without regard to the supply
voltage. This device can be used to interface 3V to 5V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note:
1. Outputs in OFF-State
outputs
■
Low Power Dissipation: I
CC
=
4µA (Max.) @ T
A
=
25°C
■
Pin and Function Compatible with 74HCT373
Ordering Information
Order Number
74VHCT373AM
74VHCT373ASJ
74VHCT373AMTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
©1997 Fairchild Semiconductor Corporation
74VHCT373A Rev. 1.3
www.fairchildsemi.com
74VHCT373A Octal D-Type Latch with 3-STATE Outputs
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Truth Table
Description
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
OE
H
L
L
L
O
n
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
©1997 Fairchild Semiconductor Corporation
74VHCT373A Rev. 1.3
www.fairchildsemi.com
2
74VHCT373A Octal D-Type Latch with 3-STATE Outputs
Functional Description
The VHCT373A contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW, the latches store the information that
was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1997 Fairchild Semiconductor Corporation
74VHCT373A Rev. 1.3
www.fairchildsemi.com
3
74VHCT373A Octal D-Type Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
DC Input Voltage
DC Output Voltage
Note 2
Note 3
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Input Diode Current
Output Diode Current
(4)
DC Output Current
DC V
CC
/GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–0.5V to +7.0V
–20mA
±20mA
±25mA
±75mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(5)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
Input Voltage
Output Voltage
Note 2
Note 3
T
OPR
t
r
, t
f
Operating Temperature
Parameter
Rating
4.5V to +5.5V
0V to +5.5V
0V to V
CC
0V to 5.5V
–40°C to +85°C
0ns/V ~ 20ns/V
Input Rise and Fall Time, V
CC
=
5.0V ± 0.5V
Notes:
2. HIGH or LOW state. I
OUT
absolute maximum rating must be observed.
3. When outputs are in OFF-State or when V
CC
=
0V.
4. V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active).
5. Unused inputs must be held HIGH or LOW. They may not float.
©1997 Fairchild Semiconductor Corporation
74VHCT373A Rev. 1.3
www.fairchildsemi.com
4
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