HD-4702
March 1997
CMOS Programmable Bit Rate Generator
Description
The HD-4702 Bit Rate Generator provides the necessary clock
signals for digital data transmission systems, such as a UART. It
generates 13 commonly used bit rates using an on-chip crystal
oscillator or an external input. For conventional operation gener-
ating 16 output clock pulses per bit period, the input clock fre-
quency must be 2.4576MHz (i.e. 9600 Baud x 16 x 16, since
there is an internal
÷
16 prescaler). A lower input frequency will
result in a proportionally lower output frequency.
The HD-4702 can provide multi-channel operation with a mini-
mum of external logic by having the clock frequency CO and the
÷
8 prescaler outputs Q0, Q1, Q2 available externally. All signals
have a 50% duty cycle except 1800 Baud, which has less than
0.39% distortion.
The four rate select inputs (S0-S3) select which bit rate is at the
output (Z). See Truth Table for Rate Select Inputs for select code
and output bit rate. Two of the 16 select codes for the HD-4702 do
not select an internally generated frequency, but select an input
into which the user can feed either a different frequency, or a static
level (High or Low) to generate “ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110, 150, 300, 1200, 2400 Baud) require that no more than one
input be grounded for the HD-4702, which is easily achieved with
a single 5-position switch.
The HD-4702 has an initialization circuit which generates a mas-
ter reset for the scan counter. This signal is derived from a digital
differentiator that senses the first high level on the CP input after
the E
CP
input goes low. When E
CP
is high, selecting the crystal
input, CP must be low. A high level on CP would apply a continu-
ous reset. See Clock Modes and Initialization below.
Features
• HD-4702 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702 Controls up to Eight Transmission
Channels
• Initialization Circuit Facilitates Diagnostic Fault
Isolation
• On-Chip Input Pull-Up Circuit
Ordering Information
PACKAGE
PDIP
CERDIP
SMD#
TEMP.
RANGE (
o
C)
-40 to +85
-40 to +85
-55 to +125
PART NUMBER
HD3-4702-9
HD1-4702-9
5962-9051801MEA
PKG. NO.
E16.3
F16.3
F16.3
Truth Table
TRUTH TABLE FOR RATE SELECT INPUTS
(Using 2.4576MHz Crystal)
S3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
S2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
OUTPUT RATE (Z)
MUX Input (IM)
MUX Input (IM)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud
Pinout
HD-4702 (CERDIP, PDIP)
TOP VIEW
Q0 1
Q1 2
Q2 3
E
CP
4
CP 5
O
X
6
I
X
7
GND 8
16 V
CC
15 I
M
14 S0
13 S1
12 S2
11 S3
10 Z
9 CO
NOTE: 19200 Baud by connecting Q2 to IM.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2954.1
5-1
HD-4702
Pin Description
PIN NUMBER
16
TYPE
SYMBOL
V
CC
GND
I
I
CP
E
CP
I
X
O
X
I
M
S0 - S3
CO
Q
0
- Q
2
Z
DESCRIPTION
V
CC
: Is the +5V power supply pin. A 0.1µF capacitor between pins 16 and 8 is
recommended for decoupling.
GROUND
EXTERNAL CLOCK INPUT
EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be
generated from the CP input.
CRYSTAL INPUT
CRYSTAL DRIVE OUTPUT
MULTIPLEXED INPUT
BAUD RATE SELECT INPUTS
CLOCK OUTPUT
SCAN COUNTER OUTPUTS
BIT RATE OUTPUT
8
5
4
7
6
15
11, 12, 13, 14
9
1, 2, 3
10
I
O
I
I
O
O
O
CLOCK MODES AND INITIALIZATION
IX
E
CP
H
X
X
X
L
H
L
H
CP
L
OPERATION
Clocked from I
X
Clocked from CP
Continuous Reset
Reset During 1st CP = High
Time
H = HIGH Level
L = LOW Level
X = Don’t Care
= Clock Pulse
= 1st HIGH Level Clock Pulse after E
CP
goes LOW
NOTE: Actual output frequency is 16 times the indicated Output
Rate, assuming a clock frequency of 2.4576MHz.
5-2
Block Diagram
(NOTE) OSCILLATOR
CIRCUIT
7
6
I
X
O
X
SCAN
COUNTER
CP
MR
COUNTER NETWORK
MULTIPLEXER
15 14 13 12 11
I
M
S0 S1 S2 S3
8
CP
MR
9600
4800
2400
1200
600
300
150
75
÷
0
CP
÷
4
4
5
E
CP
Q
MR
1
2
50
75
134.5
200
600
2400
9600
4800
D
Q
Z
FF
CP
MR
10
CP
CP
÷
18
3
Q
MR
4
5
D
Q
CP
FF
CP Q
MR
MR
÷
6
Q
MR
6
7
8
9
HD-4702
5-3
V
DD
= PIN 16
V
SS
= PIN 8
= PIN NUMBER
INITIALIZATION
CIRCUIT
CP
Q
÷
16/3MR
10 1800
11 1200
12 2400
13 300
CO
9
Q
0
Q
1
Q
2
CP
1
2
3
14 150
÷
22
Q
MR
15 110
NOTE: See Figure 4 in Design Information for Crystal Specifications.
HD-4702
Application Information
Single Channel Bit Rate Generator
Figure 1 shows the simplest application of the HD-4702. This
circuit generates one of five possible bit rates as determined by
the setting of a single pole, 5-position switch. The Bit Rate Out-
put (Z) drives one standard TTL load or four low power Schottky
loads over the full temperature range. The possible output fre-
quencies correspond to 110, 150, 300, 1200, and 2400 Baud.
For many low cost terminals, these five bit rates are adequate.
1
2
3
I
M
C
P
56pF
56pF
10M
2.4576 MHz
CRYSTAL
OUTPUT
E
CP
HD-4702
A0
D
E
93L34
A1
A2 CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
110
300
4800
1800
1200
Q
2
Z
9600
2400
150
S2
S3
Q
2
Z
S0
S1
4
S2
S3
SPST SWITCH
5
Other bit rate combinations can be generated by changing the
Scan Counter to Selector interconnection or by inserting logic
gates into this path.
I
M
C
P
56pF
56pF
10M
2.4576 MHz
CRYSTAL
E
CP
S0
S1
S2
S3
HD-4702
†
I
X
O
X
C
O
Q
0
Q
1
Q
2
Z
†
I
X
O
X
C
O
Q
0
Q
1
†
See Table 1.
FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH
EIGHT SIMULTANEOUS FREQUENCIES
†
See Table 1.
19200 Baud Operation
SWITCH POSITION
1
2
3
4
5
HD-4702 BIT RATE
110 Baud
150 Baud
300 Baud
1200 Baud
2400 Baud
Though a 19200 Baud signal is not internally routed to the mul-
tiplexer, the HD-4702 can be used to generate this bit rate by
connecting the Q
2
output to IM input and applying select code.
An additional 2-input NOR gate can be used to retain the “Zero
Baud” feature on select code 1 for the HD-4702 (See Figure 3).
FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES
Simultaneous Generation of Several Bit Rates
Figure 2 shows a simple scheme that generates eight bit rates
on eight output lines, using one HD-4702 and one 93L34 Bit
Addressable Latch. This and the following applications take
advantage of the built-in scan counter (prescaler) outputs. As
shown in the block diagram, these outputs (Q
0
to Q
2
) go
through a complete sequence of eight states for every half-
period of the highest output frequency (9600 Baud). Feeding
these Scan Counter Outputs back to the Select Inputs of the
multiplexer causes the HD-4702 to interrogate sequentially
eight different frequency signals. The 93L34 8-bit addressable
Latch, addressed by the same Scan Counter Outputs, re-con-
verts the multiplexed single Output (Z) of the HD-4702 into
eight parallel output frequency signals. In the simple scheme of
Figure 2, input S3 is left open (HIGH) and the following bit rates
are generated:
Q0: 110 Baud
Q3: 1800 Baud
Q6: 300 Baud
Q1: 9600 Baud
Q4: 1200 Baud
Q7: 150 Baud
Q2: 4800 Baud
Q5: 2400 Baud
56pF
56pF
10M
2.4576 MHz
CRYSTAL
I
M
C
P
E
CP
S0
S1
HD-4702
†
I
X
O
X
C
O
Q
0
Q
1
OUTPUT
†
See Table 1.
FIGURE 3. 19200 BAUD OPERATION
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETERS
Frequency
Series Resistance (Max)
Unwanted Modes
Type of Operation
Load Capacitance
TYPICAL CRYSTAL SPEC
2.4576MHz “AT” Cut
250
-6.0dB (Min)
Parallel
32pF +0.5
5-4
HD-4702
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Typical Derating Factor . . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance (Typical)
θ
JA
θ
JC
o
C/W
CERDIP Package . . . . . . . . . . . . . .
78
23
o
C/W
PDIP Package . . . . . . . . . . . . . . . . .
90
o
C/W
N/A
o
C to +150
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HD-4702-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
HD-4702-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
DC Electrical Specifications
V
CC
= 5V
±10%,
T
A
= -40
o
C to +85
o
C (HD-4702-9), T
A
= -55
o
C to +125
o
C (HD-4702-8)
LIMITS
SYMBOL
V
IH
V
IL
V
OH1
V
OL1
I
IH
I
ILX
I
IL
I
OHX
I
OH1
I
OH2
I
OLX
I
OL
I
CC
PARAMETER
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
(l
X
Input)
Input Low Current
(All Other Inputs)
Output High Current
(O
X
)
Output High Current
(All Other Outputs)
Output High Current
(All Other Outputs)
Output Low Current
(O
X
)
Output Low Current
(All Other Outputs)
Supply Current
(Static)
MIN
V
CC
70%
-
V
CC
-0.1
-
-1
-1
-
-0.1
-1.0
-0.3
0.1
1.6
-
-
MAX
-
V
CC
30%
-
0.1
+1
+1
-100
-
-
-
-
-
1500
1000
UNITS
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
V
CC
= 4.5V
V
CC
= 4.5V
TEST CONDITIONS
I
OH
≤
-1µA, V
CC
= 4.5V, (Note 1)
I
OL
≤
+1µA, V
CC
= 4.5V, (Note 1)
V
IN
= V
CC
, All 0ther Pins = 0V, V
CC
= 5.5V
V
IN
= 0V, All Other Pins = V
CC
, V
CC
= 5.5V
V
IN
= 0V, All Other Pins = V
CC
, V
CC
= 5.5V
(Note 2)
V
OUT
= V
CC
- 0.5, V
CC
= 4.5V, Input at 0V
or V
CC
per Logic Function or Truth Table
V
OUT
= 2.5V, V
CC
= 4.5V, Input at 0V
or V
CC
per Logic Function or Truth Table
V
OUT
= V
CC
-0.5, V
CC
= 4.5V, Input at 0V
or V
CC
per Logic Function or Truth Table
V
OUT
= 0.4V, V
CC
= 4.5V, Input at 0V
or V
CC
per Logic Function or Truth Table
V
OUT
= 0.4V, V
CC
= 4.5V Input, at 0V
or V
CC
per Logic Function or Truth Table
E
CP
= V
CC
, CP = 0V, V
CC
= 5.5V,
All Other Inputs = GND, (Note 2)
E
CP
= V
CC
, CP = 0V, V
CC
= 5.5V,
All Other Inputs = V
CC
, (Note 2)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs
except I
X
.
5-5
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