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74VHC132 — Quad 2-Input NAND Schmitt Trigger
December 2007
74VHC132
Quad 2-Input NAND Schmitt Trigger
Features
■
High Speed: t
PD
=
3.9ns (Typ.) at V
CC
=
5V
■
Power down protection is provided on all inputs
■
Low power dissipation: I
CC
=
2µA (Max.) at T
A
=
25°C
■
Low noise: V
OLP
=
0.8V (Max.)
■
Pin and function compatible with 74HC132
General Description
The VHC132 is an advanced high speed CMOS 2-input
NAND Schmitt Trigger Gate fabricated with silicon gate
CMOS technology. It achieves the high-speed operation
similar to Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Pin configuration and
function are the same as the VHC00 but the inputs have
hysteresis between the positive-going and negative-
going input thresholds, which are capable of transform-
ing slowly changing input signals into sharply defined,
jitter-free output signals. Thus greater noise margin then
conventional gates is provided. An input protection
circuit ensures that 0V to 7V can be applied to the input
pins without regard to the supply voltage. This device
can be used to interface 5V to 3V systems and two
supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
74VHC132M
74VHC132SJ
74VHC132MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
www.fairchildsemi.com
74VHC132 — Quad 2-Input NAND Schmitt Trigger
Connection Diagram
Logic Diagram
Pin Description
Pin Names
A
n
, B
n
Y
n
Inputs
Outputs
Description
Truth Table
A
L
L
H
H
B
L
H
L
H
Y
H
H
H
L
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
www.fairchildsemi.com
2
74VHC132 — Quad 2-Input NAND Schmitt Trigger
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
www.fairchildsemi.com
3
74VHC132 — Quad 2-Input NAND Schmitt Trigger
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
P
T
A
=
–40°C to
+85°C
Max.
2.20
3.15
3.85
Parameter
Positive Threshold
Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
Typ.
Min.
Max.
2.20
3.15
3.85
Units
V
V
N
Negative Threshold
Voltage
0.90
1.35
1.65
0.30
0.40
0.50
V
IN
=
V
IH
or V
IL
I
OH
=
–50µA
1.9
2.9
4.4
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
or V
IL
I
OL
=
50µA
2.58
3.94
0.0
0.0
0.0
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
0.1
0.1
0.1
0.36
0.36
±0.1
2.0
2.0
3.0
4.5
1.20
1.40
1.60
0.90
1.35
1.65
0.30
0.40
0.50
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
20.0
1.20
1.40
1.60
V
V
H
Hysteresis Output
Voltage
V
V
OH
HIGH Level Output
Voltage
V
V
OL
LOW Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
V
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
0–5.5
5.5
µA
µA
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Maximum
Dynamic V
OL
Maximum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Typ.
0.3
–0.3
Limits
0.8
–0.8
3.5
1.5
Units
V
V
V
V
Note:
2. Parameter guaranteed by design.
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
www.fairchildsemi.com
4
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