74VHC112 Dual J-K Flip-Flops with Preset and Clear
September 1995
Revised April 1999
74VHC112
Dual J-K Flip-Flops with Preset and Clear
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to transition time. The J and K inputs can
change when the clock is in either state without affecting
the flip-flop, provided that they are in the desired state dur-
ing the recommended setup and hold times relative to the
falling edge of the clock. The LOW signal on PR or CLR
prevents clocking and forces Q and Q HIGH, respectively.
Simultaneous LOW signals on PR and CLR force both Q
and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High speed: f
MAX
= 200 MHz (typ) at V
CC
= 5.0V
s
Low power dissipation: I
CC
= 2
µA
(max) at T
A
= 25°C
s
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Pin and function compatible with 74HC112
Ordering Code:
Order Number
74VHC112M
74VHC112SJ
74VHC112MTC
74VHC112N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
J
1
, J
2
, K
1
, K
2
CLK
1
, CLK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
2
, Q
1
, Q
2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
Outputs
Description
© 1999 Fairchild Semiconductor Corporation
DS012123.prf
www.fairchildsemi.com
74VHC112
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−0.5V
to V
CC
+
0.5V
−20
mA
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
±
0.3V
V
CC
=
5.0V
±
0.5V
0
∼
100 ns/V
0
∼
20 ns/V
2.0V to
+5.5V
0V to
+5.5V
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
−
5.5
2.0
3.0
−
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
−
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
2.0
2.0
3.0
4.5
T
A
=
25°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
20.0
V
µA
µA
I
OL
=
4 mA
I
OL
=
8 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
V
I
OH
= −4
mA
I
OH
= −8
mA
V
IN
=
V
IH
I
OL
=
50
µA
or V
IL
V
Typ
Max
T
A
= −40°C
to
+85°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
Max
Units
V
V
V
IN
=
V
IH
I
OH
= −50 µA
or V
IL
Conditions
3
www.fairchildsemi.com
74VHC112
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock
Frequency
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
Time (CP to Q
n
or Q
n
)
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay Time
(PR or CLR to Q
n
or Q
n
)
5.0
±
0.5
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Note 3:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
/4 (per F/F), and the total C
PD
when n pcs of the Flip-Flop operate can
be calculated by the following equation: C
PD
(total)
=
30
+
14 • n
V
CC
(V)
3.3
±
0.3
T
A
=
25°C
Min
110
90
150
120
Typ
150
120
200
185
8.5
10.0
5.1
6.3
6.7
9.7
4.6
6.4
4
18
11.0
15.0
7.3
10.5
10.2
13.5
6.7
9.5
10
Max
T
A
= −40°C
to
+85°C
Min
100
80
135
110
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.4
16.5
8.8
12.0
11.7
15.0
8.0
11.0
10
Max
Units
MHz
MHz
ns
ns
ns
ns
pF
pF
Conditions
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 3)
3.3
±
0.3
3.3
±
0.3
AC Operating Requirements
Symbol
t
W
t
S
t
H
t
REC
Minimum Pulse Width
(CP or CLR or PR)
Minimum Setup Time
(J
n
or K
n
to CP
n
)
Minimum Hold Time
(J
n
or K
n
to CP
n
)
Minimum Recovery Time
(CLR or PR to CP)
Note 4:
V
CC
is 3.3
±
0.3V or 5.0
±
0.5V
Parameter
V
CC
(Note 4)
(V)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
T
A
=
25°C
Typ
T
A
= −40°C
to
+85°C
Guaranteed Minimum
5.0
5.0
5.0
4.0
1.0
1.0
6.0
5.0
5.0
5.0
5.0
4.0
1.0
1.0
6.0
5.0
Units
ns
ns
ns
ns
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