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74AC373, 74ACT373 — Octal Transparent Latch with 3-STATE Outputs
January 2008
74AC373, 74ACT373
Octal Transparent Latch with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Eight latches in a single package
■
3-STATE outputs for bus interfacing
■
Outputs source/sink 24mA
■
ACT373 has TTL-compatible inputs
General Description
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Ordering Information
Order Number
74AC373SC
74AC373SJ
74AC373MTC
74AC373PC
74ACT373SC
74ACT373SJ
74ACT373MSA
74ACT373MTC
74ACT373PC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20D
MSA20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
www.fairchildsemi.com
74AC373, 74ACT373 — Octal Transparent Latch with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Functional Description
The AC/ACT373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard
outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Truth Table
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
OE
H
L
L
L
O
n
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition
of Latch Enable
©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
www.fairchildsemi.com
2
74AC373, 74ACT373 — Octal Transparent Latch with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
www.fairchildsemi.com
3
74AC373, 74ACT373 — Octal Transparent Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
= −
0.5V
V
I
=
V
CC
+
0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
−
0.5V to
+
7.0V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
−
20mA
+
20mA
−
0.5V to V
CC
+
0.5V
±
50mA
±
50mA
−
65
°
C to
+
150
°
C
140
°
C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
www.fairchildsemi.com
4
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