74F162A Synchronous Presettable BCD Decade Counter
April 1988
Revised January 2004
74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 74F162A is a high-speed synchronous decade counter
operating in the BCD (8421) sequence. They are synchro-
nously presettable for applications in programmable divid-
ers. The F162A has a Synchronous Reset input that
overrides counting and parallel loading and allows all out-
puts to be simultaneously reset on the rising edge of the
clock. The F162A is a high speed version of the F162.
Features
s
Synchronous counting and loading
s
High-speed synchronous expansion
s
Typical count rate of 120 MHz
Ordering Code:
Order Number
74F162ASC
74F162APC
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbols
74F162A
74F162A
74F162A
© 2004 Fairchild Semiconductor Corporation
DS009485
www.fairchildsemi.com
74F162A
Unit Loading/Fan Out
U.L.
Pin Names
CEP
CET
CP
SR
P
0
–P
3
PE
Q
0
–Q
3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
−
1 mA/20 mA
−
1 mA/20 mA
Functional Description
The 74F162A count modulo-10 in the BCD (8421)
sequence. From state 9 (HLLH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
occur as a result of, and synchronous with, the LOW-to-
HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: synchronous reset, parallel load, count-up and hold.
Four control inputs— Synchronous Reset (SR), Parallel
Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET)—determine the mode of operation,
as shown in the Mode Select Table. A LOW signal on SR
overrides counting and parallel loading and allows all out-
puts to go LOW on the next rising edge of CP. A LOW sig-
nal on PE overrides counting and allows information on the
Parallel Data (P
n
) inputs to be loaded into the flip-flops on
the next rising edge of CP. With PE and SR HIGH, CEP
and CET permit counting when both are HIGH. Conversely,
a LOW signal on either CEP or CET inhibits counting.
The F162A uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the F568 datasheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the F162A decade
counters, the TC output is fully decoded and can only be
HIGH in state 9. If a decade counter is preset to an illegal
state, or assumes an illegal state when power is applied, it
will return to the normal sequence within two counts, as
shown in the State Diagram.
Logic Equations:
Count Enable
=
CEP
×
CET
×
PE
TC
=
Q
0
×
Q
1
×
Q
2
×
Q
3
×
CET
Mode Select Table
SR
L
H
H
H
H
PE
X
L
H
H
H
CET CEP
X
X
H
L
X
X
X
H
X
L
Action on the Rising
Clock Edge (
Reset (Clear)
Load (P
n
→
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
)
State Diagram
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
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2
74F162A
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
I
IL
I
OS
I
CC
Input LOW
Current
Output Short-Circuit Current
Power Supply Current
−60
37
4.75
3.75
−0.6
−1.2
−150
55
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (CP, CEP,P
n
, MR (F160A))
V
IN
=
0.5V (CET, SR (F162A), PE)
V
OUT
=
0V
V
O
=
HIGH
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