74F161A, 74F163A Synchronous Presettable Binary Counter
April 2007
74F161A, 74F163A
Synchronous Presettable Binary Counter
Features
■
Synchronous counting and loading
■
High-speed synchronous expansion
■
Typical count frequency of 120MHz
tm
General Description
The 74F161A and 74F163A are high-speed synchro-
nous modulo-16 binary counters. They are synchro-
nously presettable for application in programmable
dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming
synchronous multi-stage counters. The 74F161A has an
asynchronous Master-Reset input that overrides all other
inputs and forces the outputs LOW. The 74F163A has a
Synchronous Reset input that overrides counting and
parallel loading and allows the outputs to be simulta-
neously reset on the rising edge of the clock. The
74F161A and 74F163A are high-speed versions of the
74F161 and 74F163.
Ordering Information
Order
Number
74F161ASC
74F161ASJ
74F161APC
74F163ASC
74F163ASJ
74F163APC
Package
Number
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagrams
74F161A
74F163A
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
74F161A, 74F163A Synchronous Presettable Binary Counter
Logic Symbols
74F161A
IEEE/IEC
74F163A
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Pin Names
CEP
CET
CP
MR (74F161A)
SR (74F163A)
P
0
–P
3
PE
Q
0
–Q
3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
U.L.
HIGH / LOW
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 1.0
1.0 / 2.0
1.0 / 1.0
1.0 / 2.0
50 / 33.3
50 / 33.3
Input I
IH
/ I
IL
Output I
OH
/ I
OL
20µA / -0.6mA
20µA / -1.2mA
20µA / -0.6 mA
20µA / -0.6 mA
20µA / -1.2 mA
20µA / -0.6 mA
20µA / -1.2mA
-1mA / 20mA
-1mA / 20mA
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
2
74F161A, 74F163A Synchronous Presettable Binary Counter
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven
in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the 74F161A)
occur as a result of, and synchronous with, the LOW-to-
HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: asynchronous reset (74F161A), synchronous
reset (74F163A), parallel load, count-up and hold. Five
control inputs—Master Reset (MR, 74F161A), Synchro-
nous Reset (SR, 74F163A), Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET)—
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel load-
ing and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (P
n
) inputs to be
loaded into the flip-flops on the next rising edge of CP.
With PE and MR ('F161A) or SR (74F163A) HIGH, CEP
and CET permit counting when both are HIGH. Con-
versely, a LOW signal on either CEP or CET inhibits
counting.
The 74F161A and 74F163A use D-type edge triggered
flip-flops and changing the SR, PE, CEP and CET inputs
when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement syn-
chronous multi-stage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the 74F568 data sheet. The TC output is
subject to decoding spikes due to internal race condi-
tions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or
registers.
Logic Equations:
Count Enable = CEP • CET • PE
TC = Q
0
• Q
1
• Q
2
• Q
3
• CET
Mode Select Table
SR
(1)
L
H
H
H
H
PE
X
L
H
H
H
Action on the Rising
CET CEP
Clock Edge ( )
X
X
H
L
X
X
X
H
X
L
Reset (Clear)
Load (P
n
→
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note:
1. For 74F163A only
State Diagram
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
3
74F161A, 74F163A Synchronous Presettable Binary Counter
Block Diagram
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
Figure 1.
www.fairchildsemi.com
4
74F161A, 74F163A Synchronous Presettable Binary Counter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
CC
V
IN
I
IN
V
O
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage
(2)
Input Current
(2)
Voltage Applied to Output in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output in LOW State (Max.)
ESD Last Passing Voltage (Min.)
Rating
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
–0.5V to V
CC
–0.5V to +5.5V
twice the rated I
OL
(mA)
4000V
Note:
2. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
Free Air Ambient Temperature
Supply Voltage
Parameter
Rating
0°C to +70°C
+4.5V to +5.5V
©1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Rev. 1.0.2
www.fairchildsemi.com
5
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