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74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
September 1991
Revised March 2005
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
The ABT245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input deter-
mines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
Features
s
Bidirectional non-inverting buffers
s
A and B output sink capability of 64 mA, source
capability of 32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch-free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time is less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT245CSC
74ABT245CSJ
74ABT245CMSA
74ABT245CMTC
74ABT245CMTCX_NL
(Note 1)
74ABT245CPC
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS010945
www.fairchildsemi.com
74ABT245
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
OE
T/R
A
0
–A
7
B
0
–B
7
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Truth Table
Inputs
OE
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Output
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH Z State
Logic Diagram
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2
74ABT245
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Any Output
in the Disabled or
Power-off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs
500 mA
10V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
2.5
2.0
0.55
1
1
I
BVI
I
BVIT
I
IL
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (I/O)
Input LOW Current
7
100
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
V
Min
Min
Min
Min
Max
Max
Max
Max
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA (OE, T/R)
3 mA (A
n
, B
n
)
32 mA (A
n
, B
n
)
64 mA (A
n
, B
n
)
2.7V (OE, T/R)
V
CC
(OE, T/R)
7.0V (OE, T/R)
5.5V (A
n
, B
n
)
0.5V (OE, T/R)
0.0V (OE, T/R)
1.9
P
A (OE, T/R)
P
A
P
A
P
A
P
A
V
1
1
4.75
V
ID
I
IH
I
OZH
I
IL
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Input Leakage Test
All Other Pins Grounded
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional
I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
No Load
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
Max
0.0
Max
Max
Max
V
OUT
V
OUT
V
OUT
2.7V (A
n
, B
n
); OE
0.5V (A
n
, B
n
); OE
0.0V (A
n
, B
n
)
V
CC
(A
n
, B
n
)
5.5V (A
n
, B
n
);
2.0V
2.0V
10
100
275
50
100
50
30
50
2.5
2.5
50
0.1
P
A
P
A
P
A
mA
All Others GND
All Outputs HIGH
All Outputs LOW
OE
V
I
Max
V
CC
, T/R
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
GND or V
CC
;
P
A
mA
mA
All Other GND or V
CC
OE, T/R V
I
Data Input V
I
Outputs Open
OE
GND, T/R
GND or V
CC
One Bit Toggling, 50% Duty Cycle
P
A
mA/
MHz
All Others at V
CC
or GND.
Max
3
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74ABT245
DC Electrical Characteristics
(SOIC package)
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Min
Typ
0.7
Max
1.0
Units
V
V
V
V
0.6
V
V
CC
5.0
5.0
5.0
5.0
5.0
T
A
T
A
T
A
T
A
T
A
Conditions
C
L
50 pF, R
L
500
:
25
q
C (Note 4)
25
q
C (Note 4)
25
q
C (Note 6)
25
q
C (Note 5)
25
q
C (Note 5)
1.3
2.7
2.0
1.0
3.1
1.7
0.9
Note 4:
Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5:
Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 6:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Data to Outputs
Output Enable
Time
Output Disable
Time
1.0
1.0
1.5
1.5
1.0
1.0
V
CC
C
L
25
q
C
5V
50 pF
Typ
2.1
2.4
3.2
3.7
3.6
3.3
Max
3.6
3.6
6.0
6.0
6.1
5.6
T
A
55
q
C to
125
q
C
V
CC
C
L
Min
1.0
1.0
1.0
2.0
1.7
1.7
4.5V–5.5V
50 pF
Max
4.8
4.8
6.7
7.5
7.4
6.5
T
A
40
q
C to
85
q
C
4.5V–5.5V
50 pF
Max
3.6
3.6
6.0
6.0
6.1
5.6
ns
ns
ns
Units
C
L
V
CC
Min
1.0
1.0
1.5
1.5
1.0
1.0
Extended AC Electrical Characteristics
(SOIC package)
40
q
C to
85
q
C
V
CC
Symbol
Parameter
C
L
4.5V–5.5V
50 pF
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
C
L
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
Units
C
L
V
CC
V
CC
8 Outputs Switching
(Note 7)
Min
f
TOGGLE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Max Toggle Frequency
Propagation Delay
Data to Outputs
Output Enable Time
1.5
1.5
1.5
1.5
1.0
1.0
Typ
100
5.0
5.0
6.5
6.5
6.5
5.6
Max
1 Output Switching
(Note 8)
Min
1.5
1.5
2.5
2.5
(Note 10)
Max
6.0
6.0
7.5
7.5
8 Outputs Switching
(Note 9)
Min
2.5
2.5
2.5
2.5
Max
MHz
8.5
8.5
9.5
11.0
(Note 10)
ns
ns
ns
Note 7:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10:
The 3-STATE delays are dominated by the RC network (500
:
, 250 pF) on the output and have been excluded from the datasheet.
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