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74ALVCH16244T

产品描述ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48
产品类别逻辑   
文件大小219KB,共10页
制造商ST(意法半导体)
官网地址http://www.st.com/
标准
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74ALVCH16244T概述

ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48

74ALVCH16244T规格参数

参数名称属性值
是否Rohs认证符合
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
Reach Compliance Codecompliant
控制类型ENABLE LOW
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
长度12.5 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.024 A
位数4
功能数量4
端口数量2
端子数量48
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源3.3 V
Prop。Delay @ Nom-Sup3 ns
传播延迟(tpd)5.1 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
宽度6.1 mm
Base Number Matches1

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74ALVCH16244
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 3.0 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.7 ns (MAX.) at V
CC
= 2.3 to 2.7V
t
PD
= 5.1 ns (MAX.) at V
CC
= 1.65V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 2.3V
|I
OH
| = I
OL
= 4mA (MIN) at V
CC
= 1.65V
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
BUS HOLD PROVIDED ON DATA INPUTS
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16244
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74ALVCH16244TTR
PIN CONNECTION
DESCRIPTION
The 74ALVCH16244 is a low voltage CMOS 16
BIT BUS BUFFER (NON INVERTED) fabricated
with sub-micron silicon gate and five-layer metal
wiring C
2
MOS technology. It is ideal for low power
and very high speed 1.65 to 3.6V applications; it
can be interfaced to 3.6V signal environment for
both inputs and outputs.
Any nG output control governs four BUS
BUFFERS. Output Enable input (nG) tied together
gives full 16-bit operation.
When nG is LOW, the outputs are enabled. When
nG is HIGH, the output are in high impedance
state.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
1/10

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