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74ALVCH16373
Low-Voltage 16-Bit
Transparent Latch with Bus
Hold 1.8/2.5/3.3 V
(3–State, Non–Inverting)
The 74ALVCH16373 is an advanced performance, non–inverting
16–bit transparent latch. It is designed for very high–speed, very
low–power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16373 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Latch Enable inputs. These control pins can be tied together for
full 16–bit operation.
The 74ALVCH16373 contains 16 D–type latches with 3–state
3.6 V–tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH–to–LOW transition of LE. The 3–state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The data inputs include active bushold circuitry,
eliminating the need for external pull–up resistors to hold unused or
floating inputs at a valid logic state.
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MARKING DIAGRAM
48
48
74ALVCH16373DT
1
AWLYYWW
TSSOP–48
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN NAMES
Pins
OEn
LEn
D0–D15
O0–O15
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
•
Designed for Low Voltage Operation: VCC = 1.65 – 3.6 V
•
3.6 V Tolerant Inputs and Outputs
•
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
•
•
3.9 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
Static Drive:
±24
mA Drive at 3.0 V
±18
mA Drive at 2.3 V
±6
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V
†
Near Zero Static Supply Current in All Three Logic States (20
µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
±250
mA @ 125°C
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
Second Source to Industry Standard 74ALVCH16373
ORDERING INFORMATION
Device
74ALVCH16373DT
74ALVCH16373DTR
Package
TSSOP
TSSOP
Shipping
39 Units/Rail
2500/Tape & Reel
†To ensure the outputs activate in the 3–state condition, the output enable pins
should be connected to VCC through a pull–up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
©
Semiconductor Components Industries, LLC, 2001
1
November, 2001 – Rev. 0
Publication Order Number:
74ALVCH16373/D
74ALVCH16373
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
VCC 7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
VCC 18
O12 19
O13 20
GND 21
O14 22
O15 23
OE2 24
48 LE1
47 D0
46 D1
45 GND
44 D2
43 D3
42 VCC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 VCC
30 D12
29 D13
D1
OE1
LE1
D0
1
48
47
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
Q
2
O0
OE2
LE2
D8
24
25
36
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
Q
13
O8
46
Q
3
O1
D9
35
Q
14
O9
D2
44
Q
5
O2
D10
33
Q
16
O10
D3
43
Q
6
O3
D11
32
Q
17
O11
D4
41
Q
8
O4
D12
30
Q
19
O12
D5
40
Q
9
O5
D13
29
Q
20
O13
28 GND
27 D14
26 D15
25 LE2
D6
38
Q
11
O6
D14
27
Q
22
O14
D7
37
Q
12
O7
D15
26
Q
23
O15
Figure 1. 48–Lead Pinout
(Top View)
Figure 2. Logic Diagram
OE1
LE1
48
25
LE2
24
OE2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
EN1
EN2
EN3
EN4
1
1
∇
2
∇
1
1
3
∇
1
4
∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
Figure 3. IEC Logic Diagram
Inputs
LE1
X
H
H
L
OE1
H
L
L
L
D0:7
X
L
H
X
Outputs
O0:7
Z
L
H
O0
LE2
X
H
H
L
Inputs
OE2
H
L
L
L
D8:15
X
L
H
X
Outputs
O8:15
Z
L
H
O0
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
ICC reasons, DO NOT FLOAT Inputs. O0 = No Change.
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2
74ALVCH16373
MAXIMUM RATINGS
(Note 1)
Symbol
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
TL
TJ
q
JA
MSL
FR
VESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% – 35%
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
VI < GND
VO < GND
Parameter
Value
*0.5
to
)4.6
*0.5
to
)4.6
*0.5
to
)4.6
*50
*50
$50
$100
$100
*65
to
)150
260
)150
90
Level 1
UL–94–VO (0.125 in)
u2000
u200
N/A
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
ILATCH–UP Latch–Up Performance
Above VCC and Below GND at 85_C (Note 6)
$250
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
VO
TA
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free–Air Temperature
Input Transition Rise or Fall Rate
VCC = 2.5 V
$
0.2 V
VCC = 3.0 V
$
0.3 V
VCC = 5.0 V
$
0.5 V
Parameter
Operating
Data Retention Only
(Note 7)
(HIGH or LOW State)
Min
2.3
1.5
0
0
*40
0
0
0
Max
3.6
3.6
3.6
3.6
)85
20
10
5
Unit
V
V
V
_C
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
74ALVCH16373
DC ELECTRICAL CHARACTERISTICS
TA =
*40_C
to
)85_C
Symbol
VIH
Parameter
HIGH Level Input Voltage
(Note 8)
(
)
1.65 V
v
VCC
t
2.3 V
2.3 V
v
VCC
v
2.7 V
2.7 V
t
VCC
v
3.6 V
VIL
LOW Level Input Voltage
(Note 8)
(
)
1.65 V
v
VCC
t
2.3 V
2.3 V
v
VCC
v
2.7 V
2.7 V
t
VCC
v
3.6 V
VOH
HIGH Level Output Voltage
1.65 V
v
VCC
v
3.6 V; IOH =
*100
mA
VCC = 1.65 V; IOH =
*4
mA
VCC = 2.3 V; IOH =
*6
mA
VCC = 2.3 V; IOH =
*12
mA
VCC = 2.7 V; IOH =
*12
mA
VCC = 3.0 V; IOH =
*12
mA
VCC = 3.0 V; IOH =
*24
mA
VOL
LOW Level Output Voltage
1.65 V
v
VCC
v
3.6 V; IOL = 100
mA
VCC = 1.65 V; IOL = 4 mA
VCC = 2.3 V; IOL = 6 mA
VCC = 2.3 V; IOL = 12 mA
VCC = 2.7 V; IOL = 12 mA
VCC = 3.0 V; IOL = 24 mA
VOL
II
II(HOLD)
LOW Level Output Voltage
Input Leakage Current
Minimum Bus–hold Input
Current
VCC = 3.6 V; VI = 0 to 3.6 V
1.65 V
v
VCC
v
3.6 V; 0 V
v
VI
v
3.6 V
VCC = 3.0 V, VIN = 0.8 V
VCC = 3.0 V, VIN = 2.0 V
VCC = 2.3 V, VIN = 0.7 V
VCC = 2.3 V, VIN = 1.7 V
VCC = 1.65 V, VIN = 0.58 V
VCC = 1.65 V, VIN = 1.07 V
IOZ
IOFF
ICC
3–State Output Current
Power–Off Leakage Current
Quiescent Supply Current
(Note 9)
(N
)
1.65 V
v
VCC
v
3.6 V; 0 V
v
VO
v
3.6 V; VI = VIH or VIL
VCC = 0 V; VI or VO = 3.6 V
1.65 V
v
VCC
v
3.6 V; VI = GND or VCC
1.65 V
v
VCC
v
3.6 V; 3.6 V
v
VI, VO
v
3.6 V
75
*75
45
*45
25
*25
$10
10
40
$40
750
mA
mA
mA
mA
VCC
*
0.2
1.20
2.0
1.7
2.2
2.4
2.0
0.2
0.45
0.4
0.7
0.4
0.55
$500
$5.0
mA
mA
mA
V
Condition
0.65
1.7
2.0
0.35
VCC
0.7
0.8
V
V
Min
VCC
Max
Unit
V
DI
CC
Increase in ICC per Input
2.7 V
t
VCC
≤
3.6 V; VIH = VCC
*
0.6 V
8. These values of VI are used to test DC electrical characteristics only.
9. Outputs disabled or 3–state only.
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4
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