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74ACTQ16541 16-Bit Buffer/Line Driver with 3-STATE Outputs
June 1991
Revised May 2005
74ACTQ16541
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16541 utilizes Fairchild Quiet Series
¥
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
¥
fea-
tures GTO
¥
output control for superior performance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
16-bit version of the ACTQ541
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16541SSC
74ACTQ16541MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT
¥
, Quiet Series
¥
, FACT Quiet Series
¥
and GTO
¥
are trademarks of Fairchild Semiconductor Corporation
© 2005 Fairchild Semiconductor Corporation
DS010936
www.fairchildsemi.com
74ACTQ16541
Functional Description
The ACTQ16541 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dent of the other. The control pins can be shorted together
to obtain full 16-bit operation. The 3-STATE outputs are
controlled by an Output Enable (OE
n
) input for each byte.
When OE
n
is LOW, the outputs are in 2-state mode. When
OE
n
is HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the
inputs.
Truth Tables
Inputs
OE
1
L
H
X
L
OE
2
L
X
H
L
Inputs
OE
3
L
H
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
I
0
–I
7
H
X
X
L
O
0
–O
7
H
Z
Z
L
Outputs
I
8
–I
15
H
X
X
L
O
8
–O
15
H
Z
Z
L
OE
4
L
X
H
L
Logic Diagram
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2
74ACTQ16541
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
=
0.5V
V
I
= V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Storage Temperature
0.5V to +7.0V
20 mA
+20 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
20 mA
+20 mA
40
q
C to +85
q
C
125 mV/ns
0.5V to V
CC
+ 0.5V
r
50 mA
r
50 mA
65
q
C to +150
q
C
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Max Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum
Overshoot
Minimum
V
CC
Droop
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
5.0
5.0
0.5
0.8
0.6
8.0
0.001
0.001
T
A
= +25
q
C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
T
A
=
40
q
C to +85
q
C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
V
Units
V
V
V
Conditions
V
OUT
= 0.1V
or V
CC
0.1V
V
OUT
= 0.1V
or V
CC
0.1V
I
OUT
=
50
P
A
V
IN
= V
IL
or V
IH
V
I
OH
=
24 mA
I
OH
=
24 mA (Note 2)
I
OUT
= 50
P
A
V
IN
= V
IL
or V
IH
V
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
, GND
V
I
= V
CC
2.1V
V
IN
= V
CC
or GND
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
Figure 1, Figure 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
V
V
V
V
V
V
75
0.5
V
OH
+
1.0
1.0
V
OH
+
1.5
V
OH
1.0 V
OH
1.8
1.7
1.2
2.0
0.8
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
Note 4:
Worst case package.
Note 5:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched LOW and one output held LOW.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7:
Maximum number of data inputs (n) switching. (n
1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
).
3
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74ACTQ16541
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Note 8:
Voltage Range 5.0 is 5.0V
r
0.5V.
T
A
= +25
q
C
C
L
= 50 pF
Min
3.0
2.5
2.6
2.7
2.7
2.4
Typ
5.2
4.8
5.0
5.4
5.6
5.2
Max
7.3
7.3
7.4
8.0
8.3
7.9
T
A
=
40
q
C to +85
q
C
C
L
= 50 pF
Min
3.0
2.5
2.6
2.7
2.7
2.4
Max
7.8
7.8
7.9
8.5
8.7
8.4
ns
ns
ns
Units
Parameter
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
(V)
(Note 8)
5.0
5.0
5.0
Extended AC Electrical Characteristics
T
A
=
40
q
C to +85
q
C
C
L
= 50 pF
Symbol
Parameter
V
CC
(V)
(Note 9)
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
(Note 10)
t
OSLH
(Note 10)
t
OST
(Note 10)
Pin to Pin Skew, HL
Data to Output
Pin to Pin Skew, LH
Data to Output
Pin to Pin Skew,
LH/HL Data to Output
Output Disable Time
Propagation Delay,
Data to Output
Output Enable Time
5.0
5.0
5.0
5.0
5.0
5.0
Min
4.0
3.4
3.3
3.3
4.3
3.8
16 Outputs Switching
(Note 11)
Typ
Max
11.6
9.6
10.1
10.0
10.1
9.6
1.2
2.5
4.3
5.6
4.8
T
A
=
40
q
C to +85
q
C
C
L
= 250 pF
(Note 12)
Min
Max
14.3
13.1
(Note 13)
(Note 14)
ns
ns
ns
ns
ns
ns
Units
Note 9:
Voltage Range 5.0 is 5.0V
r
0.5V.
Note 10:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
Note 11:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 12:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 13:
3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14:
The Output Disable Time is dominated by the RC Network (500
:
, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
pF
V
CC
= 5.0V
V
CC
= 5.0V
Conditions
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