74VHC164 8-Bit Serial-In, Parallel-Out Shift Register
August 1993
Revised April 1999
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
General Description
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral-
lel-Out Shift Register. Serial data is entered through a 2-
input AND gate synchronous with the LOW-to-HIGH transi-
tion of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs
LOW independent of the clock. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
Features
s
High Speed: f
MAX
=
175 MHz at V
CC
=
5V
s
Low power dissipation: I
CC
=
4
µA
(max) at T
A
=
25°C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
s
Pin and function compatible with 74HC164
Ordering Code:
Order Number
74VHC164M
74VHC164SJ
74VHC164MTC
74VHC164N
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
A, B
CP
MR
Q
0
–Q
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Description
© 1999 Fairchild Semiconductor Corporation
DS011636.prf
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74VHC164
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the log-
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Function Table
Operating
Mode
Reset (Clear)
Shift
MR
L
H
H
H
H
Inputs
A
X
L
L
H
H
B
X
L
H
L
H
Outputs
Q
0
L
L
L
L
H
Q
1
–Q
7
L–L
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
H
=
HIGH Voltage Levels
L
=
LOW Voltage Levels
X
=
Immaterial
Q
=
Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74VHC164
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
DC Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
−0.5V
to
+7.0V
−0.5V
to
+
7.0V
−0.5V
to V
CC
+
0.5V
−20
mA
±20
mA
±25
mA
±75
mA
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
±
0.3V
V
CC
=
5.0V
±
0.5V
0 ns/V
∼
100 ns/V
0 ns/V
∼
20 ns/V
2.0V to 5.5V
0V to
+5.5V
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of circuits outside databook specifications.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level Output
Voltage
V
CC
(V)
2.0
3.0− 5.5
2.0
3.0
−
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage
Current
Quiescent Supply
Current
5.5
4.0
40.0
0
−
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
2.0
3.0
4.5
T
A
=
25°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
V
µA
µA
I
OL
=
4 mA
I
OL
=
8 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
V
V
IN
=
V
IH
or V
IL
I
OH
= −4
mA
I
OH
= −8
mA
I
OL
=
50
µA
V
Typ
Max
T
A
= −40°C
to
+85°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
Max
V
V
V
IN
=
V
IH
or V
IL
I
OH
= −50 µA
Units
Conditions
Noise Characteristics
Symbol
V
OLP
(Note 3)
V
OLV
(Note 3)
V
IHD
(Note 3)
V
ILD
(Note 3)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.0
1.5
V
C
L
=
50 pF
5.0
3.5
V
C
L
=
50 pF
5.0
−0.5
0.8
V
C
L
=
50 pF
V
CC
(V)
5.0
T
A
=
25°C
Typ
0.5
Limits
0.8
Units
V
C
L
=
50 pF
Conditions
Note 3:
Parameter guaranteed by design.
3
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74VHC164
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock Frequency
V
CC
(V)
3.3
±
0.3
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
Time (CP–Q
n
)
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
Time (MR–Q
n
)
5.0
±
0.5
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
T
A
=
25°C
Min
80
50
125
85
Typ
125
75
175
115
8.4
10.9
5.8
7.3
8.3
10.8
5.2
6.7
4
76
12.8
16.3
9.0
11.0
12.8
16.3
8.6
10.6
10
Max
T
A
= −40°C
to
+85°C
Min
65
45
105
75
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
18.5
10.5
12.5
15.0
18.5
10.0
12.0
10
Max
Units
MHz
MHz
ns
ns
ns
ns
pF
pF
Conditions
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 4)
3.3
±
0.3
3.3
±
0.3
AC Operating Requirements
Symbol
t
W
(L)
t
W
(H)
t
W
(L)
t
S
t
H
t
REC
Minimum Pulse Width (MR)
Minimum Setup Time
Minimum Hold Time
Parameter
Minimum Pulse Width (CP)
V
CC
(V)
(Note 5)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Minimum Removal Time (MR)
3.3
5.0
Note 5:
V
CC
is 3.3
±
0.3V or 5.0
±
0.5V
T
A
=
25°C
Typ
T
A
= −40°C
to
+85°C
Guaranteed Minimum
5.0
5.0
5.0
5.0
5.0
4.5
0.0
1.0
2.5
2.5
5.0
5.0
5.0
5.0
6.0
4.5
0.0
1.0
2.5
2.5
Units
ns
ns
ns
ns
ns
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4
74VHC164
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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