HMXADC9225
Radiation Hardened 12-Bit, 20 MSPS
Monolithic A/D Converter
The HMXADC9225 is a radiation hardened monolithic, single supply, 12-bit, 20
MSPS, analog-to-digital converter with an on-chip, high performance sample-and-
hold amplifier. The HMXADC9225 uses a multistage differential pipelined
architecture with output error correction logic to provide 12-bit accuracy at 20 MSPS
data rates, and guarantees no missing codes over the full operating temperature
range.
The HMXADC9225 is fabricated on a radiation hardened SOI-IV Silicon On Insulator
(SOI) process with very low power consumption.
The input of the HMXADC9225 allows for easy interfacing to space and military imaging, sensor, and communications
systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including single-
ended applications. The dynamic performance is excellent.
The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in
successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate.
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary
output format.
FEATURES
Monolithic 12-Bit, 20 MSPS A/D Converter
Rad Hard: >500k Rad(Si) Total Dose
Single +5 V Analog Supply
Complete On-Chip S/H Amplifier
Straight Binary Output Data
5V or 3.3V Digital and I/O Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.4 LSB
Signal-to-Noise and Distortion Ratio: 69.6 dB
Spurious-Free Dynamic Range: –81 dB
28-Lead Ceramic Flat Pack
Mixed Signal Rad Hard Process
The HMXADC9225 is fabricated on space qualified SOI
CMOS process. High-speed precision analog circuits
are now combined with high-density logic circuits that
can reliably withstand the harshest environments.
Space Qualified Package
The HMXADC9225 is packaged in a 28 lead ceramic flat
pack.
Low Power
The HMXADC9225 at 345 mW consumes a fraction of the
power of presently available in existing monolithic
solutions.
Output Enable (OE)
The OE input allows user to put the tri-state digital outputs
into a high impedance mode.
Dual Power Supply Capability
The HMXADC9225 uses a single +5 V power supply
simplifying system power supply design. It also features a
separate digital I/O power supply line to accommodate
3.3V and 5V logic families.
On-Chip Sample-and-Hold (SHA)
The versatile SHA input can be configured for either
single-ended or differential inputs.
HMXADC9225
BLOCK DIAGRAM
REFP, REFN
VINP
S/H
VINN
MDAC1
X16
MDAC2
X4
MDAC3
X4
Correct
Logic
Data
Output
Drivers
Output
Tri-State
Control
D0 – D11
DRVDD
DRVSS
A/D
Clock in
A/D
A/D
A/D
5
Clock
Buffer
CML
Gen
Master Bias
IREF
3
3
4
REFT
Diff
Buffer
REFB
Output
Enable
CML
AVDD
AVSS
REFCOM
RBIAS
VREF
* = 0.1 uF in parallel
with a 10uF
Cap *
0.1uF
5kΩ
External
Reference
Input
0.1uF
PIN DESCRIPTION
Pin
1
2
3-12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
CLK
BIT 12
BIT 11 – 2
BIT 1
OE
AVDD
AVSS
RBIAS
VREF INPUT
REFCOMM
REFB
REFT
CML
VINA
VINB
AVSS
AVDD
DRVSS
DRDVDD
Description
Clock Input
Least Significant Data Bit (LSB)
Data Output Bit
Most Significant Bit (MSB)
Output Enable (high active)
+5V Analog Supply
Analog Ground
Reference Current Bias Resistor
Reference Voltage Input
Reference Common
Noise Reduction Pin
Noise Reduction Pin
Common Mode Level (AVDD/2)
Analog Input (+)
Analog Input (-)
Analog Ground
+5V Analog Supply
Digital Output Driver Ground
+5V or 3.3V Digital Output Driver Supply
1 CLK
2
3
4
5
6
7
8
9
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT5
DRVDD 28
DRVSS
AVDD
27
26
AVSS 25
VIN B 24
VIN A
23
CML 22
REFT
REFB
21
20
10 BIT 4
11 BIT 3
12 BIT 2
13 BIT 1 (MSB)
14 OE
REFCOM 19
VREF IN 18
RBIAS 17
AVSS 16
AVDD 15
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HMXADC9225
SIGNAL DEFINITION
DRVDD
The Digital Output Power Supply (DRVDD) can operate
at either 5.0V or 3.3V. The DRVDD voltage defines
the interface voltage level for all the digital I/O signals
including Clock input, Output Enable, and all data
output signals.
OUTPUT ENABLE (OE)
This signal controls the electrical state of the digital
output drivers. A high logic level will enable the outputs
and a low logic level will put the output drivers into a
high impedance state.
RBIAS
R-Bias is required to create the internal bias currents.
An external resistor with a value of 5kΩ shall be
connected between pin 17 and ground.
The R-Bias resistor can also be used to change the
power consumption. By changing the resistor value,
the current consumption can be changed. The range of
this feature not yet characterized.
VOLTAGE REFERENCE INPUT
The HMXADC9225 requires the user to provide an
external voltage reference as an
INPUT
to the device.
The device is designed to operate using a 1.0V to 2.0V
external voltage reference. The input range will then be
defined by the VREF.
The full scale signal input = 2 x VREF. Signals outside
this range will be considered “out of range”.
CML (Common Mode Level)
This signal is an analog output at a value of AVDD/2. It
can be used as a reference for biasing external circuits
to a “mid-rail” value. This signal should be decoupled
with a 0.1uF capacitor.
Total Ionizing Radiation Dose
The HMXADC9225 will meet all stated functional and
electrical specifications over the entire operating
temperature range after the specified total ionizing
radiation dose. All electrical and timing performance
parameters will remain within specifications after
rebound at VDD = 5.0 V extrapolated to ten years of
operation. Total dose hardness is assured by wafer
level testing of process monitor transistors using 10
KeV X-ray and Co60 radiation sources. Transistor gate
threshold shift correlations have been made between
10 KeV X-rays applied at a dose rate of 1x10
5
rad(SiO
2
)/min at T=25°C and gamma rays (Cobalt 60
source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The HMXADC9225 will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions. Note
that the current conducted during the pulse by the ADC
inputs, outputs, and power supply may significantly
exceed the normal operating levels. The application
design must accommodate these effects.
Soft Error Rate
The HMXADC9225 is not guaranteed to operate
through an SEU or dose rate event, but it will recover
and continue to meet all specifications over the full
temperature range after an event.
Latchup and Snapback
The HMXADC9225 will not latch up due to any of the
above radiation exposure conditions when applied
under recommended operating conditions. Fabrication
with the SIMOX substrate material provides oxide
isolation between adjacent PMOS and NMOS
transistors and eliminates any potential SCR latchup
structures. Sufficient transistor body tie connections to
the p- and n-channel substrates are made to ensure no
source/drain snapback occurs.
RADIATION PERFORMANCE
ANALOG SAMPLING TIMING DIAGRAM
S1
Analog
Input
t
C
S3
t
CH
t
CL
S2
S4
Clock
Data
Out
t
OD
Data 1
3
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HMXADC9225
OUTPUT ENABLE TIMING DIAGRAM
OE
50Ω
D1-D12
85pF
TDLZ
TDHZ
(a)
TDZL
TDZH
(b)
Output Enable Timing Diagram (a) and Effective Load (b)
SWITCHING SPECIFICATIONS
(T
MIN
to T
MAX
Parameter
Clock Period (1)
Clock Pulsewidth High (46% of t
c
) (1)
Clock Pulsewidth Low (46% of t
c
) (1)
Output Delay
with AVDD = +5V, DRVDD = +5V, C
L
= 85 pF)
Symbol
t
C
t
CH
t
CL
t
OD
Min
50
23
23
3
Typ
Max
25
50
50
50
50
50
50
50
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
High Z to Output High (DRVDD=5V)
TDZH_50
3
High Z to Output Low (DRVDD=5V)
TDZL_50
3
Output High to High Z (DRVDD=5V)
TDHZ_50
3
Output Low to High Z (DRVDD=5V)
TDLZ_50
3
High Z to Output High (DRVDD=3.3V)
TDZH_33
3
High Z to Output Low (DRVDD=3.3V)
TDZL_33
3
Output High to High Z (DRVDD=3.3V)
TDHZ_33
3
Output Low to High Z (DRVDD=3.3V)
TDLZ_33
3
(1) – These are parameters of the input clock signal to the chip.
(2) – Guaranteed but not tested.
RADIATION SPECIFICATIONS
(T
MIN
to T
MAX
with AVDD = +5V, DRVDD = +5V, C
L
= 20 pF)
Parameters
Min
Max
Units
5
Total Dose Hardness
>5 x 10
Rad (Si)
12
Dose Rate Upset Hardness
>2.5 x 10
Rad(Si)/sec
12
Dose Rate Survivability
>2.5 x 10
Rad(Si)/sec
Soft Error Rate LET (1)
120
MeV cm
2
/mg
Soft Error Rate (2)
<1x10
-10
Upsets/bit-day
Latch Up
Immune
(1) The HMXADC9225 will recover and continue to meet all specifications.
(2) This error rate applies to only the logic portion of the device.
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HMXADC9225
ABSOLUTE MAXIMUM RATINGS
(AVDD = +5V, DRVDD = +5V, unless otherwise noted)
Parameters
Min
AVDD
DRVDD
AVSS
-0.3
DRVSS
-0.3
REFGND
-0.3
CLK, OE
D1-D12
VINA, VINB
VREF
REFT, REFB
Junction Temperature
NOTE: All voltages are with respect to VSS = 0V.
Max
6.5
6.5
6.5
6.5
6.5
6.5
6.5
+175
Units
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
°C
RECOMMENDED OPERATING CONDITIONS
Parameters
Min
Typ
Max
AVDD
4.75
5
5.25
DRVDD (for 5V I/O operation)
4.75
5
5.25
DRVDD (for 3.3V I/O
3.3
3.0
3.6
operation)
AVSS
-0.3
0
DRVSS
-0.3
0
REFGND
-0.3
0
CLK, OE
DRVDD + 0.5
D1-D12
5.5
VINA, VINB
0.5
4.5
VREF
1.0
2.0
REFT, REFB
5.5
Operating Temperature (case)
-55
+125
NOTE: All voltages are with respect to VSS = 0V.
Units
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
°C
ESD (Electrostatic Discharge) Sensitive
The HMXADC9225 is rated as Class I ESD. Proper ESD precautions should be taken to avoid degradation or damage
to the device.
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