A49LF040A
Preliminary
FEATURES
• Single Power Supply Operation
-
Low voltage range: 3.0 V - 3.6 V for Read and Write
Operations
• Standard Intel Low Pin Count Interface
-
Read compatible to Intel® Low Pin Count (LPC)
interface
• Memory Configuration
-
512K x 8 (4 Mbit)
• Block Architecture
-
4Mbit: eight uniform 64KByte blocks
-
Supports full chip erase for Address/Address
Multiplexed (A/A Mux) mode
•
Automatic Erase and Program Operation
-
Embedded Byte Program and Block/Chip Erase
algorithms
-
Typical 10 µs/byte programming time
-
Typical 1s block erase time
• Two Operational Modes
-
Low Pin Count Interface (LPC) Mode for in-system
operation
-
Address/Address Multiplexed (A/A Mux) Interface
Mode for programming equipment
• Low Pin Count (LPC) Mode
-
33 MHz synchronous operation with PCI bus
-
5-signal communication interface for in-system read
and write operations
-
-
-
-
-
-
-
Standard SDP Command Set
Data Polling (I/O
7
) and Toggle Bit (I/O
6
) features
Block Locking Register for all blocks
4 ID pins for multi-chip selection
5 GPI pins for General Purpose Input Register
TBL
pin for hardware write protection to Boot Block
WP
pin for hardware write protection to whole
memory array except Boot Block
• Address/Address Multiplexed (A/A Mux) Mode
-
11-pin multiplexed address and 8-pin data I/O interface
-
Supports fast programming on EPROM programmers
-
Standard SDP Command Set
-
Data Polling (I/O
7
) and Toggle Bit (I/O
6
) features
• Lower Power Consumption
-
Typical 12mA active read current
-
Typical 24mA program/erase current
•
High Product Endurance
-
Guarantee 100,000 program/erase cycles for each
block
Minimum 20 years data retention
-
• Compatible Pin-out and Packaging
-
32-pin (8 mm x 14 mm) TSOP (TYPE I)
-
32-pin PLCC
-
Optional Pb-free (Lead-free) package
-
All Pb-free (Lead-free) products are RoHS compliant
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
General Description
The A49LF040A flash memory device is designed to be
read-compatible with the Intel Low Pin Count (LPC) Interface
Specification 1.1. This device is designed to use a single low
voltage, range from 3.0 Volt to 3.6 Volt power supply to
perform in-system or off-system read and write operations. It
provides protection for the storage and update of code and
data in addition to adding system design flexibility through
five general-purpose inputs. Two interface modes are
supported by the A49LF040A: Low Pin Count (LPC) Interface
mode for In-System programming and Address/Address
Multiplexed (A/A Mux) mode for fast factory programming of
PC-BIOS applications.
The memory is divided into eight uniform 64Kbyte blocks that
can be erased independently without affecting the data in
other blocks. Blocks also can be protected individually to
prevent accidental Program or Erase commands from
modifying the memory. The boot block can be write protected
by a hardware method controlled by the
TBL
pin or a
register-based protection turned on/off by the Block Locking
Registers (LPC mode only). The rest of blocks except boot
block in the device also can be write protected by
WP
pin or
Block Locking Registers (LPC mode only). The Program and
Erase operations are executed by issuing the Program/Erase
commands into the command interface by which activating
the internal control logic to automatically process the
Program/Erase procedures. The device can be programmed
on a byte-by-byte basis after performing the Erase operation.
In addition to the Block Erase operation, the Chip Erase
feature is provided in A/A Mux mode that allows the whole
memory to be erased in one single Erase operation. The
A49LF040A provides the status detection such as Data
Polling (I/O
7
) and Toggle Bit (I/O
6
) Functions in both
FWH/LPC and A/A Mux modes. The process or completion
of Program and Erase operations can be detected by reading
the status bits.
The A49LF040A is offered in 32-lead TSOP and 32-lead
PLCC packages with optional environmental friendly lead-
free package. See Figures 1 and 2 for pin assignments and
Table 1 for pin descriptions.
PRELIMINARY (March, 2006, Version 0.1)
1
AMIC Technology, Corp.
A49LF040A
Table 1: Pin Description
Interface
A/A
Mux LPC
X
X
X
X
Symbol
A
10
-A
0
I/O
7
-I/O
0
OE
WE
Pin Name
Address
Data
Output Enable
Write Enable
Interface Mode
Select
Type
IN
I/O
IN
IN
Descriptions
Inputs for addresses during Read and Write operations in A/A Mux
mode. Row and column addresses are latched by R/ C pin.
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE is high.
To control the data output buffers.
To control the Write operations.
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, LPC mode is enabled.
This pin must be setup at power-up or before return from reset and
not change during device operation. This pin is internally pulled
down with a resistor between 20-100 K
This is the second reset pin for in-system use.
INIT
and RST
pins are internally combined and initialize a device reset when
driven low.
These four pins are part of the mechanism that allows multiple
LPC devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count strapping.
These pins are internally pulled down with a resistor between 20-
100 KΩ.
These individual inputs can be used for additional board flexibility.
The state of these pins can be read immediately at boot, through
LPC internal registers. These inputs should be at their desired
state before the start of the PCI clock cycle during which the read
is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
MODE
IN
X
X
INIT
Initialize
IN
X
ID[3:0]
Identification Inputs
IN
X
GPI[4:0]
General Purpose
Inputs
IN
X
TBL
LAD[3:0]
LCLK
LFRAME
RST
WP
R/ C
Top Block Lock
LPC Interface I/Os
Clock
Frame
Reset
Write Protect
Row/Column Select
Ready/Busy
Reserved
Power Supply
Ground
No Connection
IN
I/O
IN
IN
IN
IN
IN
OUT
X
X
X
X
X
X
X
X
X
To prevent any write operations to the Boot Block when driven low,
regardless of the state of the block lock registers. When TBL is
high it disables hardware write protection for the top Boot Block.
This pin cannot be left unconnected.
I/O Communications in LPC mode.
To provide a clock input to the device. This pin is the same as that
for the PCI clock and adheres to the PCI specifications.
To indicate start of a data transfer operation. LFRAME is also
used to abort an LPC cycle in progress.
To reset the operation of the device
When low, prevents any write operations to all but the highest
addressable block. When WP is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
This pin is used to determine if the device is busy in write
operations. Valid only in A/A Mux mode.
R/B
RES
VDD
VSS
NC
X
PWR
PWR
X
X
X
X
X
X
Reserved. These pins must be left unconnected.
To provide power supply (3.0-3.6Volt).
Circuit ground. All VSS pins must be grounded.
Unconnected pins.
Notes: IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY (March, 2006, Version 0.1)
4
AMIC Technology, Corp.
微控制器 MCU
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