Philips Semiconductors
Product specification
Quad bilateral switches
74HC4066; 74HCT4066
FEATURES
•
Very low ON-resistance:
– 50
Ω
(typical) at V
CC
= 4.5 V
– 45
Ω
(typical) at V
CC
= 6.0 V
– 35
Ω
(typical) at V
CC
= 9.0 V.
•
Complies with JEDEC standard no. 7A
•
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
GENERAL DESCRIPTION
The 74HC4066 and 74HCT4066 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4066B. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4066 and 74HCT4066 have four independent
analog switches. Each switch has two input/output pins
(pins nY or nZ) and an active HIGH enable input pin
(pin nE). When pin nE = LOW the belonging analog switch
is turned off.
The 74HC4066 and 74HCT4066 are pin compatible with
the 74HC4016 and 74HCT4016 but exhibit a much lower
on-resistance. In addition, the on-resistance is relatively
constant over the full input signal range.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
TYPICAL
SYMBOL
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
C
S
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] = sum of the outputs.
2. For 74HC4066 the condition is V
I
= GND to V
CC
.
For 74HCT4066 the condition is V
I
= GND to V
CC
−
1.5 V.
PARAMETER
turn-on time nE to V
os
turn-off time nE to V
os
input capacitance
power dissipation
capacitance per switch
maximum switch
capacitance
notes 1 and 2
CONDITIONS
74HC4066
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
11
13
3.5
11
8
74HCT4066
12
16
3.5
12
8
ns
ns
pF
pF
pF
UNIT
2004 Nov 11
2
Philips Semiconductors
Product specification
Quad bilateral switches
74HC4066; 74HCT4066
FUNCTION TABLE
See note 1.
INPUT nE
L
H
Note
1. H = HIGH voltage level.
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74HC4066N
74HCT4066N
74HC4066D
74HCT4066D
74HC4066DB
74HCT4066DB
74HC4066PW
74HCT4066PW
74HC4066BQ
74HCT4066BQ
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
1Y
1Z
2Z
2Y
2E
3E
GND
3Y
3Z
4Z
4Y
4E
1E
V
CC
DESCRIPTION
independent input/output
independent input/output
independent input/output
independent input/output
enable input (active HIGH)
enable input (active HIGH)
ground (0 V)
independent input/output
independent input/output
independent input/output
independent input/output
enable input (active HIGH)
enable input (active HIGH)
supply voltage
Fig.1
Pin configuration DIP14, SO14 and
(T)SSOP14.
2Y
2E
3E
GND
4
5
6
7
MGR253
SWITCH
off
on
PINS
14
14
14
14
14
14
14
14
14
14
PACKAGE
DIP14
DIP14
SO14
SO14
SSOP14
SSOP14
TSSOP14
TSSOP14
DHVQFN14
DHVQFN14
MATERIAL
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
CODE
SOT27-1
SOT27-1
SOT108-1
SOT108-1
SOT337-1
SOT337-1
SOT402-1
SOT402-1
SOT762-1
SOT762-1
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
−40 °C
to 125
°C
handbook, halfpage
1Y
1Z
2Z
1
2
3
14 VCC
13 1E
12 4E
4066
11 4Y
10 4Z
9
3Z
8 3Y
2004 Nov 11
3
Philips Semiconductors
Product specification
Quad bilateral switches
74HC4066; 74HCT4066
terminal 1
index area
1Z
2Z
2Y
2E
3E
2
3
4
5
6
14 V
CC
1Y
1
handbook, halfpage
13 1E
12 4E
1Y
13
1E
1Z
2Y
2Z
3Y
3Z
4Y
4Z
MGR254
1
2
4
3
8
9
11
10
4066
V
CC(1)
7
8
11 4Y
10 4Z
9
3Z
5
2E
6
3E
GND
3Y
001aac116
12
4E
Transparent top view
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic symbol.
handbook, halfpage
handbook, halfpage
1
13 #
1
X1
1
2
1
13 #
4
5 #
8
6 #
11
12 #
MGR255
2
3
4
5 #
1
X1
1
3
9
8
6 #
1
X1
1
9
10
11
12 #
1
X1
MGR256
1
10
Fig.4 IEEEC logic symbol.
2004 Nov 11
4
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