74HC4024
7-stage binary ripple counter
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024
of the 4000B series. The 74HC4024 is specified in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s
Low-power dissipation
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
3. Applications
s
Frequency dividing circuits
s
Time delay circuits.
Philips Semiconductors
74HC4024
7-stage binary ripple counter
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
f
max
C
I
C
PD
[1]
Parameter
propagation delay CP to
Q0
Conditions
C
L
= 15 pF;
V
CC
= 5 V
Min
-
-
-
Typ
14
90
3.5
25
Max
-
-
-
-
Unit
ns
MHz
pF
pF
maximum clock frequency C
L
= 15 pF;
V
CC
= 5 V
input capacitance
power dissipation
capacitance
V
I
= GND to V
CC
[1]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
5. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC4024N
74HC4024D
74HC4024DB
74HC4024PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
Type number
9397 750 13813
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 18
Philips Semiconductors
74HC4024
7-stage binary ripple counter
6. Functional diagram
Q6 3
Q5 4
Q0
12
11
9
6
5
4
3
7-STAGE
COUNTER
Q4 5
Q3 6
Q2 9
Q1 11
Q0 12
1
CP
Q1
Q2
Q3
2
MR
Q4
Q5
Q6
001aab906
CP
1
MR
2
001aab908
Fig 1. Functional diagram
Fig 2. Logic symbol
CTR7
0
1
+
CT
2
CT = 0
12
11
9
6
5
4
6
001aab907
3
Fig 3. IEC logic symbol
Q
CP
T
FF
1
T
Q
RD
MR
RD
FF
2
Q
T
Q
RD
FF
3
Q
T
Q
RD
FF
4
Q
T
Q
RD
FF
5
Q
T
Q
RD
FF
6
Q
T
Q
RD
FF
7
Q
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
001aab909
Fig 4. Logic diagram
9397 750 13813
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 18
Philips Semiconductors
74HC4024
7-stage binary ripple counter
7. Pinning information
7.1 Pinning
CP
MR
Q6
Q5
Q4
Q3
GND
1
2
3
4
5
6
7
001aab905
14 V
CC
13 n.c.
12 Q0
4024
11 Q1
10 n.c.
9
8
Q2
n.c.
Fig 5. Pin configuration
7.2 Pin description
Table 3:
Symbol
CP
MR
Q6
Q5
Q4
Q3
GND
n.c.
Q2
n.c.
Q1
Q0
n.c.
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel output 6
parallel output 5
parallel output 4
parallel output 3
ground (0 V)
not connected
parallel output 2
not connected
parallel output 1
parallel output 0
not connected
positive supply voltage
9397 750 13813
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
4 of 18
Philips Semiconductors
74HC4024
7-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4:
Input
MR
H
L
CP
X
↑
↓
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH clock transition;
↓ =
HIGH-to-LOW clock transition.
Function table
[1]
Output
Qn
L
no change
count
9. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
, I
GND
T
stg
P
tot
Parameter
supply voltage
input diode current
output diode current
output source or sink
current
V
CC
or GND current
storage temperature
power dissipation
DIP14 package
SO14, SSOP14 and
TSSOP14 packages
[1]
[2]
[1]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or
V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to V
CC
+ 0.5 V
Min
−0.5
-
-
-
-
−65
-
-
Max
+7
±20
±20
±25
±50
+150
750
500
Unit
V
mA
mA
mA
mA
°C
mW
mW
Above 70
°
C: P
tot
derates linearly with 12 mW/K.
Above 70
°
C: P
tot
derates linearly with 8 mW/K.
9397 750 13813
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
5 of 18
嵌入式系统
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