74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 03 — 20 January 2006
Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
•
74HC533; 74HCT533: but inverted outputs
•
74HC563; 74HCT563: but inverted outputs and different pin arrangement
•
74HC573; 74HCT573: but different pin arrangement
2. Features
s
3-state non-inverting outputs for bus oriented applications
s
Common 3-state output enable input
s
Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and
74HC533; 74HCT533
s
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2 000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
Philips Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
74HC373
t
PHL
, t
PLH
propagation delay
Dn to Qn
LE to Qn
C
i
C
PD
input capacitance
power dissipation
capacitance
per latch; V
I
= GND to V
CC
[1]
Parameter
Conditions
V
CC
= 5 V; C
L
= 15 pF
Min
Typ
Max
Unit
-
-
-
-
12
15
3.5
45
-
-
-
-
ns
ns
pF
pF
74HCT373
t
PHL
, t
PLH
propagation delay
Dn to Qn
LE to Qn
C
i
C
PD
[1]
V
CC
= 5 V; C
L
= 15 pF
-
-
-
per latch;
V
I
= GND to (V
CC
−
1.5 V)
[1]
14
13
3.5
41
-
-
-
-
ns
ns
pF
pF
input capacitance
power dissipation
capacitance
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Temperature range
74HC373
74HC373N
74HC373D
74HC373DB
74HC373PW
74HC373BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP20
SO20
SSOP20
TSSOP20
DHVQFN20
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
SOT146-1
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Name
Description
Version
Type number Package
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
2 of 26
Philips Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Table 2:
Ordering information
…continued
Temperature range
Name
DIP20
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
Version
SOT146-1
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number Package
74HCT373
74HCT373N
74HCT373D
−40 °C
to +125
°C
−40 °C
to +125
°C
74HCT373DB
−40 °C
to +125
°C
74HCT373PW
−40 °C
to +125
°C
74HCT373BQ
−40 °C
to +125
°C
5. Functional diagram
3
4
7
8
13
14
17
18
11
1
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
LATCH
1 TO 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae050
Fig 1. Functional diagram
OE
LE
11
3
4
7
8
13
14
17
18
LE
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
001aae048
1
11
EN
C1
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
001aae049
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 2. Logic symbol
74HC_HCT373_3
Fig 3. IEC logic symbol
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
3 of 26
Philips Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
LE
LE
LE
D
Q
LE
001aae051
Fig 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5. Logic diagram
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
4 of 26
Philips Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
74HC373
74HCT373
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
Q0
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
001aae046
74HC373
74HCT373
terminal 1
index area
2
3
4
5
6
7
8
9
GND 10
LE 11
GND
(1)
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
OE
1
D0
D1
Q1
Q2
D2
D3
Q3
GND 10
001aae047
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 6. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20
Fig 7. Pin configuration DHVQFN20
6.2 Pin description
Table 3:
Symbol
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
LE
Q4
D4
D5
74HC_HCT373_3
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
3-state output enable input (active LOW)
3-state latch output 0
data input 0
data input 1
3-state latch output 1
3-state latch output 2
data input 2
data input 3
3-state latch output 3
ground (0 V)
latch enable input (active HIGH)
3-state latch output 4
data input 4
data input 5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
5 of 26
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