SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
SN54HC175, SN74HC175
QUADRUPLE D TYPE FLIP FLOPS
WITH CLEAR
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Contain Four Flip-Flops With Double-Rail
Outputs
Typical t
pd
= 13 ns
D
±4-mA
Output Drive at 5 V
D
Low Input Current of 1
µA
Max
D
Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
SN54HC175 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature
complementary outputs from each flip-flop.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 40
SOIC − D
−40 C 85°C
−40°C to 85 C
SOP − NS
SSOP − DB
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC175N
SN74HC175D
SN74HC175DR
SN74HC175DT
SN74HC175NSR
SN74HC175DBR
SN74HC175PW
SN74HC175PWR
SN74HC175PWT
SNJ54HC175J
SNJ54HC175W
SNJ54HC175FK
SNJ54HC175J
SNJ54HC175W
SNJ54HC175FK
HC175
HC175
HC175
HC175
TOP-SIDE
MARKING
SN74HC175N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
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2Q
GND
NC
CLK
3Q
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
1Q
1D
NC
2D
2Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
CLR
NC
V
CC
4Q
4Q
4D
NC
3D
3Q
SN54HC175 . . . J OR W PACKAGE
SN74HC175 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
SN54HC175, SN74HC175
QUADRUPLE D TYPE FLIP FLOPS
WITH CLEAR
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
L
H
H
H
CLK
X
↑
↑
L
D
X
H
L
X
OUTPUTS
Q
L
H
L
Q0
Q
H
L
H
Q0
logic diagram (positive logic)
CLR
1
CLK
1D
9
4
1D
C1
R
2
1Q
1Q
3
To Three Other Channels
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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DALLAS, TEXAS 75265
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
SN54HC175, SN74HC175
QUADRUPLE D TYPE FLIP FLOPS
WITH CLEAR
recommended operating conditions (see Note 3)
SN54HC175
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC175
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
SN54HC175
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC175
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
nA
µA
pF
V
V
MAX
UNIT
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3
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
SN54HC175, SN74HC175
QUADRUPLE D TYPE FLIP FLOPS
WITH CLEAR
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
fclock
Clock frequency
4.5 V
6V
2V
CLR low
tw
Pulse duration
CLK high or low
4.5 V
6V
2V
4.5 V
6V
2V
Data
tsu
Setup time before CLK↑
CLR inactive
4.5 V
6V
2V
4.5 V
6V
2V
th
Hold time, data after CLK↑
CLK
4.5 V
6V
80
16
14
80
16
14
100
20
17
100
20
17
0
0
0
TA = 25°C
MIN
MAX
6
31
36
120
24
20
120
24
20
150
30
25
150
30
25
0
0
0
SN54HC175
MIN
MAX
4.2
21
25
100
20
17
100
20
17
125
25
21
125
25
21
0
0
0
ns
ns
ns
SN74HC175
MIN
MAX
5
25
29
MHz
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
fmax
4.5 V
6V
2V
CLR
tpd
CLK
Any
Any
4.5 V
6V
2V
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
6
31
36
12
50
60
52
15
13
58
16
13
38
8
6
150
30
26
150
30
26
75
15
13
SN54HC175
MIN
4.2
21
25
255
45
38
255
45
38
110
22
19
MAX
SN74HC175
MIN
5
25
29
190
38
32
190
38
32
90
19
16
ns
ns
MHz
MAX
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per flip-flop
TEST CONDITIONS
No load
TYP
30
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
SN54HC175, SN74HC175
QUADRUPLE D TYPE FLIP FLOPS
WITH CLEAR
PARAMETER MEASUREMENT INFORMATION
High-Level
Pulse
VCC
50%
tw
Low-Level
Pulse
VCC
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
VCC
50%
tPLH
Reference
Input
tsu
Data
Input 50%
10%
90%
50%
th
90%
VCC
50%
10% 0 V
tf
Out-of-Phase
Output
VCC
0V
In-Phase
Output
50%
10%
tPHL
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
50%
0V
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Input
tr
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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