74FR74 • 74FR1074 Dual D-Type Flip-Flop
March 1992
Revised June 2001
74FR74 • 74FR1074
Dual D-Type Flip-Flop
General Description
The 74FR74 and 74FR1074 are dual D-type flip-flops with
true and complement (Q/Q) outputs. On the 74FR74, data
at the D inputs is transferred to the outputs on the rising
edge of the clock input (CP
n
). The 74FR1074 is the nega-
tive edge triggered version of this device. Both parts fea-
ture asynchronous clear (C
Dn
) and set (S
Dn
) inputs which
are low level enabled.
Features
s
74FR74 is pin-for-pin compatible with the 74F74
s
True 150 MHz f
MAX
capability on 74FR74
s
Outputs sink 24 mA and source 24 mA
s
Guaranteed pin-to-pin skew specifications
Ordering Code:
Order Number
74FR74SC
74FR74PC
74FR1074SC
74FR1074PC
Package Number
M14A
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74FR74
74FR1074
© 2001 Fairchild Semiconductor Corporation
DS010977
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74FR74 • 74FR1074
Logic Symbols
74FR74
Pin Descriptions
Pin Names
D
n
CP
n
S
Dn
C
Dn
Q
n
Q
n
Data Inputs
Clock Inputs
Asynchronous Set Inputs
Asynchronous Clear Inputs
True Output
Complementary Output
Description
Truth Tables
74FR74
Inputs
SD
L
H
L
H
H
H
CD
H
L
L
H
H
H
CP
X
X
D
X
X
X
H
L
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
X
L
74FR1074
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
=
Rising Edge
Q
0
=
Previous Q(Q) before LOW-to-HIGH Clock Transition
74FR1074
Inputs
SD
L
H
L
H
H
H
CD
H
L
L
H
H
H
CP
X
X
D
X
X
X
H
L
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
X
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
=
Falling Edge
Q
0
=
Previous Q(Q) before HIGH-to-LOW Clock Transition
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2
74FR74 • 74FR1074
Logic Diagrams
74FR74
74FR1074
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74FR74 • 74FR1074
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
2000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OD
I
OS
I
CEX
I
CC
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
Output Circuit
Leakage Test
Output Short-Circuit Current
Output HIGH
Leakage Current
Power Supply Current
−100
−275
50
24
mA
µA
mA
Max
Max
Max
4.75
3.75
2.5
2.4
2.0
0.5
5
7
−150
−1.8
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
V
V
µA
µA
µA
mA
V
V
Min
Min
Min
Min
Min
Max
Max
Max
Max
0.0
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −24
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
IN
=
0.5V (D
n
, CP
n
)
V
IN
=
0.5V (C
Dn
, S
Dn
)
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV,
All Other Pins Grounded
V
OUT
=
0.0V
V
OUT
=
V
CC
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4
74FR74 • 74FR1074
AC Electrical Characteristics
74FR74
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
OSHL
(Note 3)
t
OSLH
(Note 3)
t
OST
(Note 3)
t
Q/Q
(Note 3)
t
PS
(Note 3)
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
Pin to Pin Skew
for HL Transitions
Pin to Pin Skew
for LH Transitions
Pin to Pin Skew
for HL/LH Transitions
True/Complement
Output Skew
Pin (Signal)
Transition Variation
150
2.5
2.5
1.5
2.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
190
3.5
4.5
3.5
5.5
5.0
6.0
5.5
7.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
150
2.5
2.5
1.5
2.0
5.0
6.0
5.5
7.0
1.0
1.0
3.0
Max
MHz
ns
ns
ns
ns
ns
Units
1.8
1.8
ns
ns
Note 3:
Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
) or in opposite directions
both HL and LH (t
OST
). t
OST
is guaranteed by design.
AC Operating Requirements
74FR74
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
C
L
=
50 pF
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
(Note 4)
t
W
(L)
t
REC
S
Dn
or C
Dn
Pulse Width
Recovery Time
S
Dn
or C
Dn
to CP
n
Note 4:
This specification is guaranteed by design.
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
2.5
2.5
0
0
3.3
3.3
Max
ns
ns
ns
Units
Max
Setup Time, HIGH or LOW
D
n
to CP
n
Hold Time, HIGH or LOW
D
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
2.5
2.5
0
0
3.3
3.3
4.0
2.0
4.0
2.0
ns
ns
5
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