74FR543 Octal Latched Transceiver with 3-STATE Outputs
January 1991
Revised May 2001
74FR543
Octal Latched Transceiver with 3-STATE Outputs
General Description
The 74FR543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Both the A and B outputs will source 15 mA and sink
64 mA.
Features
s
Functionally equivalent to 74F543
s
Back-to-back registers for storage
s
Bidirectional data path
s
A and B outputs have current sourcing capability of
15 mA and current sinking capability of 64 mA
s
Separate controls for data flow in each direction
s
Guaranteed pin-to-pin skew
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
74FR543SC
74FR543SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 2001 Fairchild Semiconductor Corporation
DS010902
www.fairchildsemi.com
74FR543
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
A
0
–A
7
B
0
–B
7
Description
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Functional Description
The 74FR543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A-to-B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from the A Port or take
data from the B Port as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on (LEAB) input
makes the A-to-B latches transparent; a subsequent LOW-
to-HIGH transition of the LEAB line puts the A latches in
the storage mode and their outputs no longer change with
the A inputs. With CEAB and OEAB both LOW, the B out-
put buffers are active and reflect the data present on the
output of the A latches. Control of data flow from B-to-A is
similar, but using the CEBA, LEBA and OEBA.
Data I/O Control Table
Inputs
CEAB LEAB OEAB
H
X
L
X
L
X
H
L
X
X
X
X
X
H
L
Latch
Status
Latched
Latched
Transparent
—
—
Output
Buffers
High Z
—
—
High Z
Driving
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
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2
74FR543
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
BVIT
I
IL
V
ID
I
OD
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
C
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Input Leakage Test
Output Circuit Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Input Capacitance
59
87
69
8.0
17.0
−100
4.75
3.75
25
−150
−225
50
100
72
102
85
2.4
2.0
0.55
5
7
100
−150
−100
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
V
µA
µA
µA
µA
µA
V
µA
µA
µA
mA
µA
µA
mA
mA
mA
pF
pF
Min
Min
Min
Min
Max
Max
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0
Max
Max
Max
5.0
5.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA
I
OH
= −3
mA (A
n
, B
n
)
I
OH
= −15
mA (A
n
, (B
n
)
I
OL
=
64 mA (A
n
, B
n
)
V
IN
=
2.7V
V
IN
=
7.0V (Control Pins)
V
IN
=
5.5V (A
n
, B
n
)
V
IN
=
0.5 (CEAB, CEBA)
V
IN
=
0.5 (LEAB, LEBA, OEAB, OEBA)
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV,
All Other Pins Grounded
V
OUT
=
2.7V (A
n
, B
n
)
V
OUT
=
0.5V (A
n
, B
n
)
V
OUT
=
0.0V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
V
OUT
=
5.25V (A
n
, B
n
)
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE
Control Pins
A
n
, B
n
3
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74FR543
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEAB to B, LEBA to A
Output Enable Time
1.3
1.3
2.3
2.3
2.3
2.3
1.6
1.6
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.0
2.6
5.7
4.0
4.3
4.9
3.9
3.5
Max
4.7
4.7
8.5
8.5
7.4
7.4
7.0
7.0
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
1.3
1.3
2.3
2.3
2.3
2.3
1.6
1.6
Max
4.7
4.7
8.5
8.5
7.4
7.4
7.0
7.0
ns
ns
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width HIGH
2.5
2.5
2.0
2.0
6.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
0.5
0.1
0.0
−0.6
3.6
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
2.5
2.5
2.0
2.0
6.0
Max
ns
ns
ns
Units
Extended AC Electrical Characteristics
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Symbol
Parameter
C
L
=
50 pF
Eight Outputs Switching
(Note 3)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
(Note 5)
t
OSLH
(Note 5)
t
OST
(Note 5)
Pin-to-Pin Skew
for HL Transitions
Pin-to-Pin Skew
for LH Transitions
Pin-to-Pin Skew
for HL/LH Transitions
3.1
1.0
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEAB to B, LEBA to A
Output Enable Time
1.3
1.3
2.3
2.3
2.3
2.3
1.6
1.6
Max
6.3
6.3
10.2
10.2
11.1
11.1
7.2
7.2
1.2
Min
3.2
3.2
4.2
4.2
Max
8.7
8.7
12.8
12.8
ns
ns
ns
ns
ns
ns
ns
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
250 pF
(Note 4)
Units
Note 3:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4:
These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 5:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW, (t
OSHL
), LOW-to-HIGH, (t
OSLH
), or HIGH-to-LOW and/or LOW-to-HIGH, (t
OST
). Specifications guaran-
teed with all outputs switching in phase.
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4
74FR543
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
5
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