• Wide power supply operating range of 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACS08E-SMD-5962-96518
• UT54ACTS08E-SMD-5962-96519
FUNCTION TABLE
INPUT
A
H
L
X
B
H
X
L
OUTPUT
Y
H
L
L
PINOUT
14-Pin Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
(3)
(6)
(8)
(11)
Y1
Y2
Y3
Y4
A2
B2
A3
B3
A4
B4
Y4
Y3
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
&
Y1
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
DESCRIPTION
The UT54ACS08E and UT54ACTS08E are quadruple two-in-
put AND gates. The circuits perform the Boolean functions Y=
A
⋅
B or
Y= A+B
in positive logic.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
1
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D2
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
j(max)
- T
c(max)
) /
Θ
jc
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum package power dissipation
permitted @ Tc=125
o
C
LIMIT
-0.3 to 6.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
15.5
±10
3.2
UNITS
V
V
°C
°C
°C
°C/W
mA
W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to +125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS08E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
V
IH
I
IN
V
OL
DESCRIPTION
Low-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 3.0V to 5.5V
V
DD
from 3.0V to 5.5V
V
IN
= V
DD
or V
SS
I
OL
= 100μA
V
DD
from 3.0V to 5.5V
V
OH
High-level output voltage
3
I
OH
= -100μA
V
DD
from 3.0V to 5.5V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS,
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS,
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
(sink)
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
(sink)
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
(source)
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
(source)
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
P
total1
Power dissipation
2, 8
C
L
= 50pF, V
DD
= 4.5V to 5.5V
1
mW/
MHz
-6
mA
-8
mA
6
mA
8
mA
-100
100
mA
-200
200
mA
V
DD
- 0.25
V
0.7 V
DD
-1
1
0.25
MIN
MAX
0.3 V
DD
UNIT
V
V
μA
V
3
P
total2
I
DDQ
Power dissipation
2, 8
Quiescent Supply Current
C
L
= 50pF, V
DD
= 3.0V to 3.6V
V
IN
= V
DD
or V
SS
V
DD
from 3.0V to 5.5V
ƒ
= 1MHz
V
DD
= 0V
ƒ
= 1MHz
V
DD
= 0V
0.5
10
mW/
MHz
μA
C
IN
Input capacitance
5
Output capacitance
5
15
pF
C
OUT
15
pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
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