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74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
March 1994
Revised May 2005
74ABT16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
Features
s
Separate control logic for each byte
s
16-bit version of the ABT374
s
Edge-triggered D-type inputs
s
Buffered Positive edge-triggered clock
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Guaranteed latch-up protection
Ordering Code:
Order Number
74ABT16374CSSC
74ABT16374CMTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Name
OE
n
CP
n
D
0
–D
15
O
0
–O
15
Description
3-STATE Output Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Inputs
3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS011668
www.fairchildsemi.com
74ABT16374
Functional Description
The ABT16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. Each
byte has a buffered clock and buffered Output Enable com-
mon to all flip-flops within that byte. The description which
follows applies to each byte. Each flip-flop will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP
n
)
transition. With the Output Enable (OE
n
) LOW, the con-
tents of the flip-flops are available at the outputs. When
OE
n
is HIGH, the outputs go to the high impedance state.
Operation of the OE
n
input does not affect the state of the
flip-flops.
Truth Tables
Inputs
CP
1
Outputs
D
0
–D
7
H
L
X
X
O
0
–O
7
H
L
(Previous)
Z
Outputs
D
8
–D
15
H
L
X
X
O
8
–O
15
H
L
(Previous)
Z
OE
1
L
L
L
H
Inputs
CP
2
L
X
L
X
OE
2
L
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
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2
74ABT16374
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current:
OE Pin
(Across Comm Operating Range)
Other Pins
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
350 mA
500 mA
10V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.55
1
1
7
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
V
Min
Min
Min
Min
Max
Max
Max
0.0
0
5.5V
0
5.5V
Max
Max
0.0
Max
Max
Max
Max
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
64 mA
2.7V (Note 3)
V
CC
7.0V
0.5V (Note 3)
0.0V
1.9
P
A
P
A
P
A
P
A
V
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
Note 4:
For 8-bit toggling, I
CCD
0.8 mA/MHz.
10
P
A
P
A
mA
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
2.7V; OE
0.5V; OE
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
2.0
62
2.0
2.5
2.5
2.5
P
A
P
A
mA
mA
mA
mA
mA
mA
mA/
5.5V; All Others V
CC
or GND
All Outputs HIGH
All Outputs LOW
OE
V
I
V
CC
; All Others at V
CC
or GND
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
Enable Input V
I
Data Input V
I
Outputs Open
OE
All Others at V
CC
or GND
No Load
0.30
MHz
Max
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74ABT16374
AC Electrical Characteristics
(SSOP Package)
T
A
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
150
1.8
1.8
1.2
1.6
2.2
2.2
6.2
5.9
5.6
5.3
7.1
6.6
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
Max
T
A
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
MHz
6.2
5.9
5.6
5.3
7.1
6.6
ns
ns
ns
C
L
Units
V
CC
Min
150
1.8
1.8
1.2
1.6
2.2
2.2
AC Operating Requirements
T
A
Symbol
Parameter
V
CC
C
L
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH
or LOW D
n
to CP
Hold Time, HIGH
or LOW D
n
to CP
Pulse Width, CP
HIGH or LOW
1.1
1.1
1.3
1.3
3.0
3.0
25
q
C
5.0V
50 pF
Max
T
A
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
ns
ns
ns
C
L
Units
V
CC
Min
1.1
1.1
1.3
1.3
3.0
3.0
Capacitance
Conditions
Symbol
C
IN
C
OUT
(Note 5)
Parameter
Input Capacitance
Output Capacitance
Typ
5.0
11.0
1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
V
CC
V
CC
0V
5.0V
(T
A
25
q
C)
Note 5:
C
OUT
is measured at frequency f
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