74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25: Series Resistors in the
Outputs
June 2000
Revised June 2005
74LVTH162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
The LVTH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The LVTH162374 is designed with equivalent 25
:
series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH162374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Power Down high impedance provides
glitch-free bus loading
s
Outputs include equivalent series resistance of 25
:
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Functionally compatible with the 74 series 16374
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74LVTH162374GX
(Note 1)
74LVTH162374MEA
74LVTH162374MEX
74LVTH162374MTD
74LVTH162374MTX
Package
Number
BGA54A
(Preliminary)
MS48A
MS48A
MTD48
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
BGA package available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500355
www.fairchildsemi.com
74LVTH162374
Logic Symbol
Connection Diagrams
Pin Assignments for SSOP and TSSOP
Pin Descriptions
Pin Names
OE
n
CP
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
4
CP
1
NC
V
CC
GND
GND
GND
V
CC
NC
CP
2
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Tables
Inputs
Pin Assignment for FBGA
CP
1
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
O
o
Z
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
O
o
Z
L
X
OE
1
L
L
L
H
Inputs
CP
2
L
X
OE
2
L
L
L
H
(Top Thru View)
H
L
X
Z
O
o
HIGH Voltage Level
LOW Voltage Level
Immaterial
HIGH Impedance
Previous O
o
before HIGH-to-LOW of CP
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2
74LVTH162374
Functional Description
The LVTH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The
device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP
n
) transition. With the
Output Enable (OE
n
) LOW, the contents of the flip-flops are available at the outputs. When OE
n
is HIGH, the outputs go to
the high impedance state. Operation of the OE
n
input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
3
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74LVTH162374
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
GND
V
O
GND
V
O
!
V
CC
V
O
!
V
CC
Output at HIGH State
Output at LOW State
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
12
12
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
I(HOLD)
I
I(OD)
I
I
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.7
3.0
3.0
75
V
CC
0.2
2.0
0.2
0.8
2.0
0.8
T
A
40
q
C to
85
q
C
Max
Min
Units
V
V
V
V
V
I
I
Conditions
1.2
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OL
I
OL
V
I
V
I
100
P
A
12 mA
100
P
A
12 mA
0.8V
2.0V
75
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
500
P
A
P
A
10
(Note 4)
(Note 5)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
10
0.19
5
0.19
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
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4
74LVTH162374
DC Electrical Characteristics
Symbol
I
CCZ
Parameter
Power Supply Current
Increase in Power Supply Current
(Note 6)
(Continued)
V
CC
(V)
3.6
3.6
T
A
40
q
C to
85
q
C
Max
0.19
0.2
Units
mA
mA
Conditions
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
Min
'
I
CC
Note 4:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
Min
(Note 7)
T
A
25
q
C
Typ
0.8
Max
Conditions
Units
V
V
C
L
50 pF, R
L
(Note 8)
(Note 8)
500
:
0.8
Note 7:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
f
MAX
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Setup Time
Hold Time
Pulse Width
Output to Output Skew (Note 9)
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
160
2.0
1.6
1.8
1.2
1.9
2.0
1.8
0.8
3.0
1.0
1.0
5.1
5.3
5.0
5.6
5.0
5.4
40
q
C to
85
q
C, C
L
3.3V
r
0.3V
Max
50 pF, R
L
V
CC
Min
150
2.0
1.6
1.8
1.2
1.9
2.0
2.0
0.1
3.0
500
:
Units
2.7V
Max
MHz
5.3
6.2
6.0
6.9
5.1
5.7
ns
ns
ns
ns
ns
ns
1.0
1.0
ns
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 10)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
V
CC
V
CC
OPEN, V
I
3.0V, V
O
Conditions
0V or V
CC
0V or V
CC
Typical
4
8
Units
pF
pF
Note 10:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
5
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