White Electronic Designs
128Kx32 SRAM MODULE, SMD 5962-93187
FEATURES
Access Times of 70, 85, 100, 120ns
MIL-STD-883 Compliant Devices Available
Packaging
• 66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400).
• 68 lead, 40mm Low Profile CQFP, 3.56mm
(0.140")(Package 502).
• 68 lead, Hermetic CQFP (G2U), 22.4mm
(0.880 inch) square, 4.57mm (0.140 inch) high,
(Package 510)
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Commercial, Industrial and Military Temperature
Ranges
5V Power Supply
Low Power CMOS
WS128K32-XXX
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS128K32-XG2UX - 8 grams typical
WS128K32-XH1X - 13 grams typical
WS128K32-XG4TX - 20 grams typical
Upgradeable to 512Kx32
FIGURE 1 – PIN CONFIGURATION FOR WS128K32N-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
NC
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
NC
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
4
A
5
A
6
WE
3
#
CS
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
66
8
OE#
A
0-16
128K x 8
WE
1
# CS
1
#
Pin Description
56
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
128K x 8
128K x 8
128K x 8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
June 2004
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WS128K32-XXX
FIGURE 2 – PIN CONFIGURATION FOR WS128K32-XG4TX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
#
GND
CS
3
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Block Diagram
WE#
OE#
A
0-16
CS
1
#
CS
2
#
CS
3
#
CS
4
#
128K X 8
128K X 8
128K X 8
128K X 8
8
8
8
CS
2
#
OE#
CS
4
#
V
CC
A
12
A
13
A
14
A
15
A
16
NC
NC
NC
NC
NC
NC
A
11
NC
I/O
0 - 7
I/O
8 - 15
I/O
16 - 23
I/O
24 - 31
FIGURE 3 – PIN CONFIGURATION FOR WS128K32-XG2UX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3 2 1 68 67 66 65 64 63 62 61
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
BLOCK DIAGRAM
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
OE#
A
0-16
128K x 8
128K x 8
128K x 8
128K x 8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
June 2004
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
WS128K32-XXX
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
4.5
2.2
-0.5
Max
5.5
V
CC
+ 0.3
+0.8
Unit
V
V
V
CAPACITANCE
T
A
= +25°C
Parameter
OE# capacitance
WE
1-4
# capacitance
HIP (PGA)
CQFP G4T
CQFP G2U
CS
1-4
# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
Conditions
C
OE
V
IN
= 0V, f = 1.0 MHz
C
WE
V
IN
= 0V, f = 1.0 MHz
Max Unit
50 pF
pF
20
50
15
V
IN
= 0V, f = 1.0 MHz 20 pF
V
I/O
= 0V, f = 1.0 MHz 20 pF
V
IN
= 0V, f = 1.0 MHz 50 pF
C
CS
C
I/O
C
AD
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 2.1mA, V
CC
= 4.5
I
OH
= -1.0mA, V
CC
= 4.5
-70
Max
10
10
120
20
0.4
2.4
2.4
-85
Min
Max
10
10
120
20
0.4
2.4
-100
Min
Max
10
10
120
20
0.4
2.4
-120
Min
Max
10
10
120
20
0.4
Units
μA
μA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS
-55°C
≤
T
A
≤
+125°C
Parameter
Data Retention Supply Voltage
Data Retention Current
Sym
V
DR
I
CCDR1
Conditions
Min
CS≥V
CC
-0.2V
V
CC
= 3V
2.0
-70
Max
5.5
4
-85
Min
2.0
-100
Max
5.5
4
-120
Max
5.5
4
Units
Max
5.5
4
V
mA
Min
2.0
Min
2.0
June 2004
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
Min
70
3
70
35
3
0
25
25
3
0
25
25
-70
Max
70
3
85
45
3
0
Min
85
-85
Max
85
3
Min
100
-100
WS128K32-XXX
-120
Max
100
3
100
50
3
0
35
35
35
35
120
60
Min
120
Max
120
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
70
60
60
30
50
5
5
5
0
-70
Max
Min
85
75
75
35
55
5
5
5
0
-85
Max
Min
100
80
80
40
70
5
5
5
0
-100
Max
Min
120
100
100
50
80
5
5
5
0
-120
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
25
25
35
35
1. This parameter is guaranteed by design but not tested.
FIGURE. 4 – AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
(Bipolar Supply)
V
Z
1.5V
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ½.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
June 2004
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIGURE 5 – TIMING WAVEFORM - READ CYCLE
WS128K32-XXX
CS#
OE#
READ CYCLE 2, (CS# = OE# = V
IL
, WE# = V
IH
)
READ CYCLE 2 (WE# = V
IH
)
FIGURE 6 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
FIGURE 7 – WRITE CYCLE - CS# CONTROLLED
WS32K32-XHX
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
June 2004
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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