WS128K32-XXX / EDI8C32128C
HI-RELIABILITY PRODUCT
128Kx32 SRAM MODULE, SMD 5962-93187 & 5962-95595
FEATURES
s
Access Times of 15, 17, 20, 25, 35, 45, 55ns
s
MIL-STD-883 Compliant Devices Available
s
Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400)
• 68 lead, 40mm Low Profile CQFP, 3.56mm (0.140")
(Package 502), Package to be developed.
• 68 lead, 22.4mm Low Profile CQFP, 4.57mm (0.180"),
(Package 509)
s
Organized as 128Kx32; User Configurable as 256Kx16 or
512Kx8
s
Low Power Data Retention - only available in G2T/E
package type
s
s
s
s
s
Commercial, Industrial and Military Temperature Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight:
WS128K32-XG2TX / EDI8C32128C-E - 8 grams typical
WS128K32-XH1X / EDI8C32128C-G - 13 grams typical
WS128K32-XG4TX - 20 grams typical
s
All devices are upgradeable to 512Kx32
NOTE:
For non-SMD new designs, please use the WS128K32-
XXX part number for inquiries and orders.
FIG. 1
PIN CONFIGURATION FOR WS128K32N-XH1X
AND EDI8C32128C-G
TOP VIEW
PIN DESCRIPTION
34
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
WE
1
CS
1
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
23
56
I/O
0-31
Data Inputs/Outputs
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
OE
A
0-16
I/O
22
I/O
21
128K x 8
128K x 8
128K x 8
128K x 8
I/O
20
66
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
August 1999 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS128K32-XXX /
EDI8C32128C
FIG. 2
PIN CONFIGURATION FOR WS128K32-XG4TX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-16
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
WE
CS
1-4
OE
V
CC
GND
NC
BLOCK DIAGRAM
CS
1
WE
OE
A
0
-
16
128K x 8
128K x 8
CS
2
CS
3
CS
4
128K x 8
128K x 8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
NC
NC
NC
NC
NC
NC
NC
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
FIG. 3
PIN CONFIGURATION FOR WS128K32-XG2TX
AND EDI8C32128C-E
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-16
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
WE
1-4
CS
1-4
OE
0.940"
V
CC
GND
The White 68 lead G2T CQFP
NC
Not Connected
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE
and lead inspection advantage
BLOCK DIAGRAM
of the CQFP form.
WE
1
CS
1
WE
2
CS
2
WE
3
CS
3
OE
A
0-16
128K x 8
WE
4
CS
4
WE
2
WE
3
WE
4
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
OE
NC
CS
1
CS
2
NC
NC
NC
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WS128K32-XXX /
EDI8C32128C
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
X
H
L
H
TRUTH TABLE
WE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA) H1/G
CQFP G4
CQFP G2T/E
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
50
20
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
Conditions
Min
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 2.1mA, V
CC
= 4.5
I
OH
= -1.0mA, V
CC
= 4.5
2.4
2.4
-15
Max
10
10
600
80
0.4
2.4
-35
Max
10
10
600
60
0.4
2.4
Min
-17
Min Max
10
10
600
80
0.4
2.4
-45
Max
10
10
600
60
0.4
2.4
Min
Min
-20
Max
10
10
600
80
0.4
2.4
-55
Max
10
10
600
60
0.4
Min
-25
Max
10
10
600
60
0.4
Units
µA
µA
mA
mA
V
V
Units
µA
µA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS*
(T
A
= -55°C to +125°C), (T
A
= -40°C to +85°C)
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Sym
V
CC
I
CCDR
T
CDR
T
R
Conditions
V
CC
= 2.0V
CS
≥
V
CC
-0.2V
V
IN
≥
V
CC
-0.2V
or V
IN
≤
0.2V
Min
2
-
0
T
RC
Typ
-
1
-
Max
-
4
-
-
Units
V
mA
ns
ns
NOTE: Parameter guaranteed, but not tested.
*Low Power Data Retention available only in G2T/E Package Type.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS128K32-XXX /
EDI8C32128C
AC CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
t
CHZ
1
Symbol
-15
Min
15
15
0
15
10
3
0
12
12
3
0
0
Max
-17
Min
17
17
0
17
10
3
0
12
12
Max Min
20
-20
Max
Min
25
20
0
20
12
3
0
12
12
-25
Max
Min
35
25
0
25
15
3
0
12
12
-35
Max
Min
45
35
0
35
20
3
0
20
20
-45
Max
-55
Min
55
45
0
45
25
3
0
20
20
20
20
55
30
55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
t
DH
1
Symbol
Min
15
14
14
10
14
0
0
3
-15
Max
17
14
15
10
14
0
0
3
10
0
0
-17
Min
Max
Min
20
15
15
12
15
0
0
3
10
0
-20
Max
Min
25
20
20
15
20
0
0
3
12
0
-25
Max
35
25
25
20
25
0
0
4
15
0
-35
Min
Max
Min
45
30
30
25
30
0
0
4
20
0
-45
Max
Min
-55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
WS128K32-XXX /
55
EDI8C32128C
45
45
25
45
0
0
4
25
0
t
WHZ
1
1. This parameter is guaranteed by design but not tested.
FIG. 4
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WS128K32-XXX /
EDI8C32128C
FIG. 5
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
RC
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
FIG. 6
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 7
WRITE CYCLE - CS CONTROLLED
ADDRESS
t
WC
WS32K32-XHX
t
AS
t
AW
t
CW
t
AH
CS
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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