74VHC161284 IEEE 1284 Transceiver
February 1998
Revised June 2005
74VHC161284
IEEE 1284 Transceiver
General Description
The VHC161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r
14 mA). The pull-up and pull-
down series termination resistance of these outputs on the
cable side is optimized to drive an external cable. In addi-
tion, all inputs (except HLH) and outputs on the cable side
contain internal pull-up resistors connected to the V
CC
sup-
ply to provide proper termination and pull-ups for open
drain mode.
Outputs on the Peripheral side are standard LOW-drive
CMOS outputs. The DIR input controls data flow on the A
1
–
A
8
/B
1
–B
8
transceiver pins.
Features
s
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s
Replaces the function of two (2) 74ACT1284 devices
s
All inputs have hysteresis to provide noise margin
s
B and Y output resistance optimized to drive external
cable
s
B and Y outputs in high impedance mode during power
down
s
Inputs and outputs on cable side have internal pull-up
resistors
s
Flow-through pin configuration allows easy interface
between the Peripheral and Host
Ordering Code:
Ordering Number Package Number
74VHC161284MEA
74VHC161284MTD
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 2005 Fairchild Semiconductor Corporation
DS500098
www.fairchildsemi.com
74VHC161284
Absolute Maximum Ratings
(Note 3)
Supply Voltage
V
CC
Input Voltage (V
I
) (Note 4)
A
1
–A
13
, PLH
IN
, DIR, HD
B
1
–B
8
, C
14
–C
17
, HLH
IN
B
1
–B
8
, C
14
–C
17
, HLH
IN
Output Voltage (V
O
)
A
1
–A
8
, A
14
–A
17
, HLH
B
1
–B
8
, Y
9
–Y
13
, PLH
B
1
–B
8
, Y
9
–Y
13
, PLH
DC Output Current (I
O
)
A
1
–A
8
, HLH
B
1
–B
8
, Y
9
–Y
13
PLH (Output LOW)
PLH (Output HIGH)
Input Diode Current (I
IK
) (Note 4)
DIR, HD, A
9
–A
13
,
PLH, HLH, C
14
–C
17
Output Diode Current (I
OK
)
A
1
–A
8
, A
14
–A
17
, HLH
B
1
–B
8
, Y
9
–Y
13
, PLH
DC Continuous V
CC
or
Ground Current
Storage Temperature
ESD (HBM) Last Passing
Voltage
2000V
Recommended Operating
Conditions
Supply Voltage
V
CC
DC Input Voltage (V
I
)
Open Drain Voltage (V
O
)
Operating Temperature (T
A
)
4.5V to 5.5V
0V to V
CC
0V to 5.5V
0.5V to
7.0V
0.5V to V
CC
0.5V
0.5V to
5.5V (DC)
2.0V to
7.0V *
*40 ns Transient
40
q
C to
85
q
C
0.5V to V
CC
0.5V
0.5V to
5.5V (DC)
2.0V to
7.0V*
*40 ns Transient
r
25 mA
r
50 mA
84 mA
50 mA
20 mA
r
50 mA
50 mA
r
200 mA
65
q
C to
150
q
C
Note 3:
Absolute Maximum continuos ratings are those values beyond
which damage to the device may occur. Exposure to these indicated may
adversely affect device reliability. Functional operation under absolute max-
imum rated conditions is not implied.
Note 4:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IK
V
IH
Input Clamp Diode Voltage
Minimum HIGH Level Input Voltage
A
n
, PLH
IN
, DIR, HD
B
n
C
n
HLH
IN
V
IL
Maximum LOW Level Input Voltage
A
n
, PLH
IN
, DIR, HD
B
n
C
n
HLH
IN
Parameter
V
CC
(V)
3.0
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.0
5.0
4.5
4.5
B
n
, Y
n
PLH
4.5
4.5
T
A
40
q
C to
85
q
C
1.2
0.7 V
CC
2.0
2.3
2.6
0.3 V
CC
0.8
0.8
1.6
0.4
0.4
0.8
0.3
4.4
3.8
3.73
4.45
Units
V
I
I
Conditions
Guaranteed Limits
18 mA
V
V
'
VT
Minimum Input Hysteresis
A
n
, PLH
IN
, DIR, HD
B
n
C
n
HLH
IN
V
V
T
–V
T
V
T
–V
T
V
T
–V
T
V
T
–V
T
I
OH
V
OH
Minimum HIGH Level Output Voltage
A
n
, HLH
50
P
A
8 mA
14 mA
500
P
A
V
I
OH
I
OH
I
OH
3
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74VHC161284
DC Electrical Characteristics
Symbol
V
OL
Parameter
Maximum LOW Level Output Voltage
(Continued)
V
CC
(V)
4.5
4.5
4.5
4.5
5.0
5.0
5.0
5.0
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
0.0
0.0
0.0
5.5
HIGH).
T
A
40
q
C to
85
q
C
0.1
0.44
0.77
0.7
55
35
1650
1150
1.0
100
Units
Conditions
I
OL
50
P
A
8 mA
14 mA
84 mA
Guaranteed Limits
I
OL
I
OL
I
OL
A
n
, HLH
B
n
, Y
n
PLH
V
RD
RP
I
IH
I
IL
I
OZH
I
OZL
I
OFF
I
OFF
I
OFF
I
CC
I
CC
Maximum Output Impedance
Minimum Output Impedance
Maximum Pull-Up Resistance
Minimum Pull-Up Resistance
Maximum Input Current in HIGH State
Maximum Input Current in LOW State
Maximum Output Disable Current
(HIGH)
Maximum Output Disable Current
(LOW)
Power Down Output Leakage
Power Down Input Leakage
Power Down Leakage to V
CC
Maximum Supply Current
B
1
–B
8
, Y
9
–Y
13
B
1
–B
8
, Y
9
–Y
13
B
1
–B
8
, Y
9
–Y
13
, C
14
–C
17
B
1
–B
8
, Y
9
–Y
13
, C
14
–C
17
A
9
–A
13
, PLH
IN
, HD, DIR, HLH
IN
C
14
–C
17
A
9
–A
13
, PLH
IN
, HD, DIR, HLH
IN
C
14
–C
17
A
1
—A
8
B
1
–B
8
A
1
—A
8
B
1
–B
8
B
1
–B
8
, Y
9
–Y
13
, PLH
C
14
–C
17
, HLH
IN
:
:
:
:
P
A
P
A
mA
(Note 5)(Note 6)
(Note 5)(Note 6)
V
I
V
I
V
I
V
I
V
O
V
O
V
O
V
O
V
I
V
I
5.5V
5.5V
0.0V
0.0V
5.5V
5.5V
0.0V
5.5V
5.5V
V
CC
or GND
1.0
5.0
20
100
P
A
P
A
mA
20
5.0
100
100
250
70
P
A
P
A
P
A
mA
(Note 7)
Note 5:
Output impedance is measured with the output active LOW and active HIGH (HD
Note 6:
This parameter is guaranteed but not tested, characterized only.
Note 7:
Power-down leakage to V
CC
is tested by simultaneously forcing all pins on the cable-side (B
1
–B
8
, Y
9
–Y
13
, PLH, C
14
–C
17
and HLH
IN
to 5.5V and
measuring the resulting I
CC
.
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4
74VHC161284
AC Electrical Characteristics
T
A
Symbol
Parameter
40
q
C to
85
q
C
4.5V
5.5V
Max
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
6.0
30.0
30.0
30.0
30.0
18.0
18.0
25.0
25.0
25.0
25.0
28.0
28.0
20.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5
Figure 4
Figure 6
(Note 10)
Figure 1
Figure 2
Figure 3
Figure 3
Figure 1
Figure 2
Figure 3
Figure 3
(Note 9)
Figure 1
Figure 2
Figure 3
Figure 3
Figure 7
Figure 8
Figure 9
Figure 2
Figure 2
Units
Figure
Number
V
CC
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
SKEW
t
PHL
t
PLH
t
PHL
t
PLH
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
t
pEN
t
pDis
t
pEn
–t
pDis
t
SLEW
t
PLH
t
PHL
t
r
, t
f
A
1
–A
8
to B
1
–B
8
A
1
–A
8
to B
1
–B
8
B
1
–B
8
to A
1
–A
8
B
1
–B
8
to A
1
–A
8
A
9
–A
13
to Y
9
–Y
13
A
9
–A
13
to Y
9
–Y
13
C
14
–C
17
to A
14
–A
17
C
14
–C
17
to A
14
–A
17
LH-LH or HL-HL
PLH
IN
to PLH
PLH
IN
to PLH
HLH
IN
to HLH
HLH
IN
to HLH
Output Disable Time
DIR to A
1
–A
8
Output Enable Time
DIR to A
1
–A
8
Output Disable Time
DIR to B
1
–B
8
Output Enable Time
HD to B
1
–B
8
, Y
9
–Y
13
Output Disable Time
HD to B
1
–B
8
, Y
9
–Y
13
Output Enable-Output Disable
Output Slew Rate
B
1
–B
8
, Y
9
–Y
13
t
RISE
and t
FALL
B
1
–B
8
, Y
9
–Y
13
(Note 8)
0.05
0.05
0.40
0.40
120
120
V/ns
ns
Note 8:
Open Drain
Note 9:
t
SKEW
is measured for common edge output transitions and compares the measured propagation delay for a given path type.
(i) A
1
–A
8
to B
1
–B
8
, A
9
–Y
13
to Y
9
–Y
13
(ii) B
1
–B
8
to A
1
–A
8
(iii) C
14
–C
17
to A
14
–A
17
Note 10:
This parameter is guaranteed but not tested, characterized only.
Capacitance
(Note 11)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
I/O Pin Capacitance
1 MHz.
Typ
5
12
Units
pF
pF
V
CC
V
CC
3.3V
Conditions
0.0V (HD, DIR, A
9
—A
13
, C
14
—C
17
, PLH
IN
and HLH
IN
)
Note 11:
Capacitance is measured at frequency
5
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