Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 88AP303-A1-BGF2C624-TN22

文档预览

88AP303-A1-BGF2C624-TN22: 产品描述RISC Microprocessor, 624MHz, CMOS, PBGA409, 19 X 19 MM, 0.80 MM PITCH, VFBGA-409; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小4MB，共214页; 制造商Marvell(美满科技); 官网地址http://www.marvell.com; 标准

下载文档详细参数全文预览

88AP303-A1-BGF2C624-TN22概述

RISC Microprocessor, 624MHz, CMOS, PBGA409, 19 X 19 MM, 0.80 MM PITCH, VFBGA-409

88AP303-A1-BGF2C624-TN22规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Marvell(美满科技)
零件包装代码	BGA
包装说明	LFBGA, BGA409,23X23,32
针数	409
Reach Compliance Code	compliant
地址总线宽度
边界扫描	YES
最大时钟频率	13.002 MHz
外部数据总线宽度
格式	FLOATING POINT
集成缓存	YES
JESD-30 代码	S-PBGA-B409
长度	19 mm
低功率模式	YES
端子数量	409
最高工作温度	85 °C
最低工作温度	-25 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFBGA
封装等效代码	BGA409,23X23,32
封装形状	SQUARE
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH
电源	1.8/3.3 V
认证状态	Not Qualified
座面最大高度	1.56 mm
速度	624 MHz
表面贴装	YES
技术	CMOS
温度等级	OTHER
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
宽度	19 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

Cover

Marvell

PXA3xx

(88AP3xx) Processor

Family

Electrical, Mechanical, and Thermal

Functional Specification

PXA30x Processor (88AP300, 88AP301, 88AP302, 88AP303)

PXA31x Processor (88AP310, 88AP311, 88AP312)

PXA32x Processor (88AP320, 88AP322)

Doc. No. MV-S105156-00,

Rev. 2.0 Version -

April 6, 2009 Released

Marvell.

Moving Forward Faster

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Document Conventions

Note:

Provides related information or information of special importance.

Caution:

Indicates potential damage to hardware or software, or loss of data.

Warning:

Indicates a risk of personal injury.

Document Status

Draft

Preliminary

Tapeout

(Advance)

Preliminary

Information

For internal use. This document has not passed a complete technical review cycle and ECN signoff

process.

This document contains design specifications for a product in its initial stage of design and development.

A revision of this document or supplementary information may be published at a later date.

Marvell may make changes to these specifications at any time without notice.

Contact Marvell Field Application Engineers for more information.

This document contains preliminary specifications.

A revision of this document or supplementary information may be published at a later date.

Marvell may make changes to these specifications at any time without notice. .

Contact Marvell Field Application Engineers for more information.

This document contains specifications for a product in its final qualification stages.

Marvell may make changes to these specifications at any time without notice.

Contact Marvell Field Application Engineers for more information.

X.YZ

Work in Progress Indicator

Zero means document is released.

Various Revisions Indicator

Technical Publication: 3.10

Complete

Information

Milestone Indicator:

Draft = 0.xx

Advance = 1.xx

Preliminary = 2.xx

Complete = 3.xx

Doc Status:

For more information, visit our website at:

www.marvell.com

Disclaimer

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,

without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any

kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any

particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.

Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use

Marvell products in these types of equipment or applications.

With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:

1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control

Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;

2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are

controlled for national security reasons by the EAR; and,

3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,

not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons

by the EAR, or is subject to controls under the U.S. Munitions List ("USML").

At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any

such information.

Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell.

Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All

other trademarks are the property of their respective owners.

Doc. No. MV-S105156-00 Rev. 2.0

Version -

Page 2

April 6, 2009 Released

CONTENTS

1.1

1.2

1.3

1.4

1.5

Introduction..................................................................................................................................11

Product Summary ...........................................................................................................................................11

Document Purpose .........................................................................................................................................12

Number Representation ..................................................................................................................................12

Naming Conventions .......................................................................................................................................12

Applicable Documents ....................................................................................................................................12

3.1

3.2

3.3

Functional Overview ...................................................................................................................15

Package Information ...................................................................................................................19

Introduction .....................................................................................................................................................19

Packaging Materials........................................................................................................................................19

PXA32x Processor Packaging Views..............................................................................................................19

3.3.1

PXA32x Processor 456-Ball VF-BGA Package ................................................................................19

3.3.2

PXA320 Processor Detailed Package Dimensions ..........................................................................22

3.3.3

PXA322 Processor Package-on-Package (PoP) ..............................................................................23

3.3.4

PXA322 Processor Detailed 15mm2 POP Dimensions ....................................................................28

PXA31x and PXA30x Processor Package Views............................................................................................28

3.4.1

PXA301 Processor and PXA311 Processor Multi-Chip Package (MCP)..........................................28

3.4.2

PXA301 Processor and PXA311 Processor Detailed MCP Package Dimensions ...........................32

3.4.3

PXA302 and PXA312 Processor Package-on-Package (PoP).........................................................32

3.4.4

PXA302 Processor and PXA312 Processor Detailed 15mm2 POP Dimensions..............................36

3.4.5

PXA300 Processor and PXA310 Processor Discrete Package (VF-BGA) .......................................36

PXA30x Processor Package Views ................................................................................................................40

3.5.1

PXA303 Processor 19mm2 Discrete Package (VF-BGA).................................................................40

3.5.2

PXA303 Processor Detailed VF-BGA Package Dimensions ............................................................43

PXA3xx Processor Family Markings ...............................................................................................................44

3.6.1

PXA32x Processor Markings ............................................................................................................45

3.4

3.5

3.6

4.1

Pin Listing and Signal Definitions .............................................................................................49

Ball Map View .................................................................................................................................................49

4.1.1

PXA32x Processor Ball Maps...........................................................................................................49

4.1.2

PXA31x Processor Ball Maps...........................................................................................................56

4.1.3

PXA30x Processor Ball Maps...........................................................................................................60

4.1.4

PXA30x Processor and PXA302 Processor 15mm2 Multi-Chip Package (MCP) and Package on

Package (POP) Bottom Ball Map63

4.1.5

PXA303 Processor 19mm2 VF-BGA Ball .........................................................................................64

4.1.6

PXA312 and PXA302 Package on Package (POP) Top Ball Maps .................................................67

Pin Use Tables ................................................................................................................................................68

4.2.1

PXA32x Processor Pin Use ..............................................................................................................69

4.2.2

PXA31x Processor Pin Use ..............................................................................................................87

4.2.3

PXA30x Processor Pin Use ............................................................................................................104

4.2.4

Signal Type Definitions ...................................................................................................................126

4.2

5.1

Maximum Ratings and Operation Conditions.........................................................................127

Absolute Maximum Ratings ..........................................................................................................................127

April 6, 2009 Released

Doc. No. MV-S105156-00 Rev. 2.0

Version -

Page 3

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

5.2

Operating Conditions ....................................................................................................................................128

6.1

6.2

Electrical Specifications ...........................................................................................................135

DC Voltage and Current Characteristics .......................................................................................................135

Oscillator Electrical Specifications.................................................................................................................138

6.2.1

32.768 kHz Oscillator Specifications ..............................................................................................138

6.2.2

13.000 MHz Oscillator Specifications .............................................................................................139

6.2.3

Clock Outputs .................................................................................................................................140

7.1

7.2

AC Characteristics ....................................................................................................................143

External Memory Pin Interface (EMPI) Memory Timings ..............................................................................143

7.1.1

DDR SDRAM Timing Diagrams and Specifications........................................................................144

Data-Flash Interface (DFI) Memory Timing Specifications............................................................................146

7.2.1

Variable Latency I/O (VLIO) Timing Diagrams and Specifications .................................................147

7.2.2

Flash Memory Timing Diagrams and Specifications.......................................................................152

7.2.3

SRAM Timing Diagrams and Specifications ...................................................................................159

7.2.4

Compact Flash Timing Diagrams and Specifications .....................................................................165

7.2.5

NAND Timing Diagrams and Specifications ...................................................................................168

Quick Capture Camera Interface Timing Diagrams and Specifications ........................................................173

7.3.1

Master-Parallel Timing ....................................................................................................................173

7.3.2

Master-Parallel Interface Timing Specifications..............................................................................173

7.3.3

Slave-Parallel Timing......................................................................................................................174

7.3.4

Slave-Parallel Interface Timing Parameters ...................................................................................175

LCD Timing Diagrams and Specifications.....................................................................................................175

7.4.1

LCD Passive Timing .......................................................................................................................175

7.4.2

LCD Active Panel Timing................................................................................................................177

7.4.3

LCD Smart Panel Timing ................................................................................................................179

SSP Timing Diagrams and Specifications.....................................................................................................181

7.5.1

SSP Slave Mode Timing .................................................................................................................182

7.5.2

SSP Mixed Mode Timing - Processor Master to Clock ..................................................................183

7.5.3

SSP Mixed Mode Timing - Processor Master to Frame .................................................................184

AC ’97 Timing Diagrams and Specifications .................................................................................................184

USB 2.0 Timing Diagrams and Specifications (PXA32x and PXA30x only)..................................................185

MultiMedia Card Timing Diagrams and Specifications..................................................................................186

Secure Digital (SD/SDIO) Timing Diagrams and Specifications ...................................................................187

JTAG Boundary Scan Timing Diagrams and Specifications .........................................................................188

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

8.1

8.2

Power and Reset Specifications ..............................................................................................191

Power Up Timings .........................................................................................................................................191

Powerdown Timings ......................................................................................................................................192

8.2.1

S2/D3/C4 Mode Timings.................................................................................................................192

8.2.2

S3/D4/C4 Mode Timings.................................................................................................................194

Reset Timing .................................................................................................................................................196

8.3.1

Hardware Reset Timing ..................................................................................................................196

8.3.2

Watchdog Reset Timing .................................................................................................................196

8.3.3

GPIO Reset Timing.........................................................................................................................196

Power Consumption ......................................................................................................................................197

8.3

8.4

Doc. No. MV-S105156-00 Rev. 2.0

Version -

Page 4

April 6, 2009 Released

FIGURES

Figure 1:

Figure 2:

Figure 3:

Figure 4:

Figure 5:

Figure 6:

Figure 7:

Figure 8:

Figure 9:

Figure 10:

Figure 11:

Figure 12:

Figure 13:

Figure 14:

Figure 15:

Figure 16:

Figure 17:

Figure 18:

Figure 19:

Figure 20:

Figure 21:

Figure 23:

Figure 22:

Figure 24:

Figure 25:

Figure 26:

Figure 27:

Figure 28:

Figure 29:

Figure 30:

Figure 34:

Figure 35:

Figure 40:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

Figure 45:

Figure 46:

Figure 47:

PXA32x Processor Block Diagram ...................................................................................................16

PXA31x Processor Block Diagram ...................................................................................................17

PXA30x Processor Block Diagram ...................................................................................................18

PXA320 Processor 14x14 mm VF-BGA Package, Top View ...........................................................20

PXA320 Processor 14x14 mm VF-BGA Package, Bottom View ......................................................21

PXA320 Processor 14x14 mm VF-BGA Package, Side View ..........................................................22

14x14mm VF-BGA Daisy-Chain Substrate Diagram ........................................................................22

PXA322 Processor 15-mm2 PoP Package, Top View .....................................................................24

PXA322 Processor 15-mm2 PoP Package, Bottom View ................................................................25

PXA322 Processor 15-mm2 PoP Package, Side View ....................................................................26

PXA322 15-mm2 PoP Daisy-Chain Substrate Diagram ...................................................................27

PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Top View ..............................29

PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Bottom View.........................30

PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Side View .............................31

PXA301 Processor and PXA311 Processor 15-mm2 MCP Daisy-Chain Substrate Diagram ..........31

PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Top View ...............................33

PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Bottom View ..........................34

PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Side View ..............................35

PXA302 Processor and PXA312 Processor 15-mm2 PoP Daisy-Chain Substrate Diagram............35

PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Top View.........................37

PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Bottom View ...................38

PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Daisy-Chain Substrate Diagram .....39

PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Side View........................39

PXA303 Processor 19-mm2 VF-BGA Package, Top View...............................................................41

PXA303 Processor 19-mm2 VF-BGA Package, Bottom View..........................................................42

PXA303 Processor 19-mm2 VF-BGA Package, Side View ..............................................................42

PXA303 Processor 19-mm2 VF-BGA Daisy-Chain Substrate Diagram ...........................................43

PX3xx (88AP3xx) Processor Family Product Marking Information...................................................45

PXA32x Processor VF-BGA Product Information Decoder .............................................................46

PXA32x Processor Configuration Line Decoding .............................................................................46

PXA320 Processor 14mm2 VF-BGA Ball Map, Left Half..................................................................50

PXA320 Processor 14mm2 VF-BGA Ball Map, Right Half ...............................................................51

PXA310 Processor 13mm2 VF-BGA Ball Map, Left side..................................................................57

PXA310 Processor 13mm2 VF-BGA Ball Map, Right side ...............................................................58

PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Left side .....59

PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Right

side ...................................................................................................................................................60

PXA300 Processor 13mm2 VF-BGA Ball Map, Left side..................................................................61

PXA300 Processor 13mm2 VF-BGA Ball Map, Right side ...............................................................62

PXA30x 15mm2 MCP and Package-on-Package (PoP) Bottom Ball Map, Left side .......................63

PXA30x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Right

April 6, 2009 Released

Doc. No. MV-S105156-00 Rev. 2.0

Version -

Page 5

88AP303-A1-BGF2C624-TN22

88AP303-A1-BGF2C624-TN22概述

88AP303-A1-BGF2C624-TN22规格参数

文档预览

推荐资源