1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT8737-11
÷
LOW SKEW,
÷
1/÷2 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE
(1,2)
Inputs
MR
1
0
0
0
0
CLK_EN
X
0
0
1
1
CLK_SEL
X
0
1
0
1
Selected Source
X
CLK, xCLK
PCLK, xPCLK
CLK, xCLK
PCLK, xPCLK
QA0, QA1
LOW
Disabled; LOW
Disabled; LOW
Enabled
Enabled
xQA0, xQA1
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Outputs
QB0, QB1
LOW
Disabled; LOW
Disabled; LOW
Enabled
Enabled
xQB0, xQB1
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Disabled
xCLK, xPCLK
CLK, PCLK
Enabled
≈
≈
≈
CLK_EN Timing Diagram
CLK_EN
xQA0, xQA1,
xQB0, xQB1
QA0, QA1,
QB0, QB1
CLOCK INPUT FUNCTION TABLE
(1)
Inputs
CLK or PCLK
0
1
0
1
Biased
(2)
Biased
(2)
xCLK or xPCLK
1
0
Biased
(2)
Biased
(2)
1
0
QAx
L
H
L
H
L
H
H
L
H
L
H
L
Outputs
xQAx
QBx
L
H
L
H
L
H
xQBx
H
L
H
L
H
L
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTES:
1. H = HIGH
L = LOW
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
3
IDT8737-11
÷
LOW SKEW,
÷
1/÷2 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - COMMERCIAL
Symbol
V
DD
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Min.
3.135
—
Typ.
3.3
—
Max.
3.465
50
Unit
V
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
CLK_EN, CLK_SEL, MR
CLK_EN, CLK_SEL, MR
Input Current HIGH
Input Current LOW
CLK_EN
CLK_SEL, MR
CLK_EN
CLK_SEL, MR
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Min.
2
-0.3
Typ.
Max.
V
DD
+ 0.3
0.8
5
150
μA
Unit
V
V
μA
DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL - COMMERCIAL
Symbol
V
PP
V
CMR
I
IH
I
IL
Parameter
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1,2)
Input Current HIGH
Input Current LOW
xCLK
CLK
xCLK
CLK
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Min.
0.15
V
EE
+ 0.5
Typ.
Max.
0.3
V
DD
- 0.85
5
150
μA
Unit
V
V
μA
NOTES:
1. For single-ended applications, the max. input voltage for CLK / xCLK is V
DD
+ 0.3V.
2. Common mode voltage is defined as V
IH
.
DC ELECTRICAL CHARACTERISTICS, LVPECL- COMMERCIAL
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input Current HIGH
Input Current LOW
PCLK
xPCLK
PCLK
xPCLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1,2)
Output Voltage HIGH
(3)
Output Voltage LOW
(3)
Peak-to-Peak Output Voltage Swing
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
0.3
V
EE
+ 1.5
V
DD
- 1.4
V
DD
- 2
0.65
1
V
DD
V
DD
- 1
V
DD
- 1.7
0.9
V
V
V
V
V
Min.
Typ.
Max.
5
150
μA
Unit
μA
NOTES:
1. For single-ended applications, the max. input voltage for PCLK / xPCLK is V
DD
+ 0.3V.
2. Common mode voltage is defined as V
IH
.
3. Outputs terminated with 50Ω to V
DD
- 0.2V.
4
IDT8737-11
÷
LOW SKEW,
÷
1/÷2 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
All parameters measured at 500MHz unless noted otherwise;
Cycle-to-cycle jitter = jitter on output; the part does not add jitter
Symbol
F
MAX
t
PD
t
SK
(
O
)
t
SK
(
B
)
t
SK
(
PP
)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output Skew
(2,4)
Bank Skew
(4)
Part-to-Part Skew
(3,4)
Output Rise Time
Output Fall Time
Output Duty Cycle
20 - 80% @ 50MHz
20 - 80% @ 50MHz
300
300
48
50
Bank A
Bank B
CLK, xCLK
PCLK, xPCLK
f
≤
650MHz
1
1
Test Conditions
Min.
Typ.
Max.
650
1.7
1.6
60
20
35
200
700
700
52
ps
ps
ps
%
ps
ps
Unit
MHz
ns
NOTES:
1. Measured from the differential input crossingpoint to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
POWER SUPPLY CHARACTERISTICS - INDUSTRIAL
Symbol
V
DD
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Min.
3.135
—
Typ.
3.3
—
Max.
3.465
55
Unit
V
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
CLK_EN, CLK_SEL, MR
CLK_EN, CLK_SEL, MR
Input Current HIGH
Input Current LOW
CLK_EN
CLK_SEL, MR
CLK_EN
CLK_SEL, MR
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Min.
2
-0.3
Typ.
Max.
V
DD
+ 0.3
0.8
5
150
μA
Unit
V
V
μA
DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL - INDUSTRIAL
Symbol
V
PP
V
CMR
I
IH
I
IL
Parameter
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1,2)
Input Current HIGH
Input Current LOW
xCLK
CLK
xCLK
CLK
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Min.
0.15
V
EE
+ 0.5
Typ.
Max.
1.3
V
DD
- 0.85
5
150
μA
Unit
V
V
μA
NOTES:
1. For single-ended applications, the max. input voltage for CLK / xCLK is V
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