Dual LVCMOS / LVTTL-to-Differential
HSTL Translator
G
ENERAL
D
ESCRIPTION
The 85222-01 is a Dual LVCMOS / LVTTL-to-
Differential HSTL translator. The 85222-01 has two
single ended clock inputs. The single ended clock input
accepts LVCMOS or LVTTL input levels and translates
them to HSTL levels. The small outline 8-pin SOIC package
makes this device ideal for applications where space, high
performance and low power are important.
85222-01
DATASHEET
F
EATURES
•
Two differential HSTL outputs
•
CLK0, CLK1 LVCMOS/LVTTL clock inputs
•
CLK0 and CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 350MHz
•
Part-to-part skew: 375ps (maximum)
•
Propagation delay: 1075ps (maximum)
•
V
OH
: 1.4V (maximum)
•
Full 3.3V and 2.5V operating supply voltage
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in lead-free RoHS-compliant package
B
LOCK
D
IAGRAM
CLK0
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK0
CLK1
GND
CLK1
85222-01
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
85222-01 REVISION A 5/7/15
1
©2015 Integrated Device Technology, Inc.
85222-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
CLK1
CLK0
V
DD
Output
Output
Power
Input
Input
Power
Pullup
Pullup
Type
Description
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
2
REVISION A 5/7/15
85222-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DD
I
DD
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
35
Units
V
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
CLK0, CLK1
CLK0, CLK1
CLK0, CLK1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 2.625V
V
DD
= 3.465, V
IN
= 0V
Input Low Current
CLK0, CLK1
V
DD
= 2.625, V
IN
= 0V
-150
µA
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
5
Units
V
V
µA
I
IL
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
Test Conditions
Minimum
1
0
0
0.6
0.45
Typical
Maximum
1.4
0.4
0.55
1.4
1.4
Units
V
V
V
V
V
NOTE 1: Outputs terminated with 50Ω to GND.
REVISION A 5/7/15
3
DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
85222-01 DATA SHEET
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
150MHz
150 < ƒ
≤
250MHz
250 < ƒ
≤
350MHz
150
48
46
45
700
Test Conditions
Minimum
Typical
Maximum
350
1075
375
800
52
54
55
Units
MHz
ps
ps
ps
%
%
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
≤
150MHz
150 < ƒ
≤
350MHz
150
48
46
700
Test Conditions
Minimum
Typical
Maximum
350
1200
475
800
52
54
Units
MHz
ps
ps
ps
%
%
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
4
REVISION A 5/7/15
85222-01 DATA SHEET
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ROPAGATION
D
ELAY
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
REVISION A 5/7/15
5
O
UTPUT
R
ISE
/F
ALL
T
IME
DUAL LVCMOS / LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
FPGA/CPLD
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