Dual 2:1 and 1:2 Differential-to-LVDS
Multiplexer
ICS854S54I
DATA SHEET
General Description
The ICS854S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplex-
er allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device is
useful for multiplexing multi-rate Ethernet PHYs which have 100M bit
and 1000M bit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. See Application Section for
further information.
The ICS854S54I is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
•
•
•
•
•
•
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Three differential LVDS output pairs
Three differential LVPECL clock input pairs
PCLKx pair can accept the following differential input levels:
LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Additive phase jitter, RMS: 0.053ps (typical)
Propagation delay: 480ps (maximum), QA/nQA
445ps (maximum), QBx/nQBx
Part-to-part skew: 200ps (maximum)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_SELA
Pulldown
Pin Assignment
CLK_SELA
nQA
V
DD
QA
PCLKA0
Pulldown
nPCLKA0
Pullup/Pulldown
PCLKA1
Pulldown
nPCLKA1
Pullup/Pulldown
0
QA
nQA
1
QB0 1
nQB0
2
16 15 14 13
12 PCLKA0
11 nPCLKA0
10 PCLKA1
9 nPCLKA1
5
PCLKB
QB1 3
nQB1 4
6
nPCLKB
7
CLK_SELB
8
GND
PCLKB
Pulldown
nPCLKB
Pullup/Pulldown
QB0
nQB0
ICS854S54I
CLK_SELB
Pulldown
QB1
nQB1
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS854S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.
ICS854S54I Data Sheet
DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
Name
QB0, nQB0
QB1, nQB1
PCLKB
nPCLKB
Output
Output
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Non-inverting LVPECL differential clock input.
Inverting LVPECL differential clock input. V
DD
/2 default when left floating.
Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1 outputs.
When LOW, selects QB0, nQB0 outputs. See Table 3B. LVCMOS/LVTTL
interface levels.
Power supply ground.
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Inverting LVPECL differential clock input. V
DD
/2 default when left floating.
Non-inverting LVPECL differential clock input.
Inverting LVPECL differential clock input. V
DD
/2 default when left floating.
Non-inverting LVPECL differential clock input.
Power supply pin.
Pulldown
Clock select pin for PCLKA inputs. When HIGH, selects PCLKA1/nPCLKA1
inputs. When LOW, selects PCLKA0/nPCLKA0 inputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
7
8
9
10
11
12
13
14
15, 16
CLK_SELB
GND
nPCLKA1
PCLKA1
nPCLKA0
PCLKA0
V
DD
CLK_SELA
nQA, QA
Input
Power
Input
Input
Input
Input
Power
Input
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VDD
/2
Parameter
Input Capacitance
Input Pullup Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
37.5
37.5
Maximum
Units
pF
k
k
Function Tables
Table 3A. Control Input Function Table, Bank A
Bank A
Control Input
CLK_SELA
0 (default)
1
Outputs
QA, nQA
Selects PCLKA0, nPCLKA0
Selects PCLKA1, nPCLKA1
Control Input
CLK_SELB
0 (default)
1
QB0, nQB0
Follows PCLKB input
Logic Low
Table 3B. Control Input Function Table, Bank B
Bank B
Outputs
QB1, nQB1
Logic Low
Follows PCLKB input
ICS854S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.
ICS854S54I Data Sheet
DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
82
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SELA,
CLK_SELB
CLK_SELA,
CLK_SELB
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-10
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
ICS854S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.
ICS854S54I Data Sheet
DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4C. DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
-40°C
Symbol
Parameter
Input
High Current
PCLKAx,
PCLKB,
nPCLKx,
nPCLKB
PCLKAx,
PCLKB,
nPCLKAx,
nPCLKB
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Units
I
IH
150
150
150
µA
I
IL
Input
Low Current
-10
-10
-10
µA
V
PP
V
CMR
Peak-to-peak Input
Voltage; NOTE 1
Common Mode Input
Voltage; NOTE 1, 2
0.15
1.2
1.2
V
DD
0.15
1.2
1.2
V
DD
0.15
1.2
1.2
V
DD
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH.
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
-40°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
0.95
1.2
Min
350
Typ
450
Max
550
50
1.4
50
0.95
1.2
Min
350
25°C
Typ
450
Max
550
50
1.4
50
0.95
1.2
Min
350
85°C
Typ
450
Max
550
50
1.4
50
Units
mV
mV
V
mV
NOTE: Refer to Parameter Measurement Information,
2.5V Output Load Test Circuit diagram.
ICS854S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.
ICS854S54I Data Sheet
DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section; NOTE 2
QA, nQA
QBx, nQBx
QA, nQA
QBx, nQBx
622.08MHz, Integration
Range: 12kHz - 20MHz
622.08MHz, Integration
Range: 12kHz - 20MHz
20% to 80%
QA, nQA
QBx, nQBx
ƒ
OUT
= 622.08MHz,
V
PP
= 400mV
55
47
47
65
225
200
0.053
0.045
200
265
53
53
Test Conditions
Minimum
Typical
Maximum
2.5
480
445
Units
GHz
ps
ps
ps
ps
ps
ps
%
%
dB
tjit
tsk(pp)
t
R
/ t
F
odc
MUX_
ISOLATION
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation; NOTE 5
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at
1.35GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured using clock input at 622.08MHz.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in Parameter Measurement Information section.
ICS854S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.
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